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31. 发明授权

US07398361B2 Combined buffer for snoop, store merging, load miss, and writeback operations 有权
标题翻译：组合缓冲区，用于侦听，存储合并，加载错误和回写操作
公开(公告)号：US07398361B2
公开(公告)日：2008-07-08
申请号：US11215604
申请日：2005-08-30
申请人： Ramesh Gunna , Po-Yung Chang , Sridhar P. Subramanian , James B. Keller , Tse-Yuh Yeh
发明人： Ramesh Gunna , Po-Yung Chang , Sridhar P. Subramanian , James B. Keller , Tse-Yuh Yeh
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.
摘要翻译：在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接收的窥探请求的地址。所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中第一个队列。响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址第二个队列中的缓冲区条目。

32. 发明申请

US20080086623A1 Strongly-ordered processor with early store retirement 有权
标题翻译：处理器处理器处于早期退休状态
公开(公告)号：US20080086623A1
公开(公告)日：2008-04-10
申请号：US11546074
申请日：2006-10-10
申请人： Wei-Han Lien , Po-Yung Chang
发明人： Wei-Han Lien , Po-Yung Chang
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
摘要： In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
摘要翻译：在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。

33. 发明授权

US08285937B2 Fused store exclusive/memory barrier operation 有权
标题翻译：融合商店独家/内存屏障操作
公开(公告)号：US08285937B2
公开(公告)日：2012-10-09
申请号：US12711941
申请日：2010-02-24
申请人： Peter J. Bannon , Po-Yung Chang
发明人： Peter J. Bannon , Po-Yung Chang
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/522 , G06F9/526 , G06F2209/521
摘要： In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.
摘要翻译：在一个实施例中，处理器可以被配置为在由处理器执行的推测性指令流中检测存储排他操作，随后进行存储器障碍操作。处理器可以融合存储专有操作和存储器屏障操作，创建融合操作。可以传输和全局排序融合操作，并且响应于融合操作，处理器可以完成存储排他操作和存储器屏障操作两者。当融合操作通过处理器和一个或多个其它组件（例如高速缓存层级中的高速缓存）进行到系统中的订购点时，融合操作可以推动先前的存储器操作来实现存储器屏障操作。在一些实施例中，如果存储排他操作在订购点成功，则可以减少完成存储排他操作和后续数据存储器屏障操作的等待时间。

34. 发明申请

US20110208915A1 Fused Store Exclusive/Memory Barrier Operation 有权
标题翻译：融合商店独家/内存障碍操作
公开(公告)号：US20110208915A1
公开(公告)日：2011-08-25
申请号：US12711941
申请日：2010-02-24
申请人： Peter J. Bannon , Po-Yung Chang
发明人： Peter J. Bannon , Po-Yung Chang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/522 , G06F9/526 , G06F2209/521
摘要： In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.
摘要翻译：在一个实施例中，处理器可以被配置为在由处理器执行的推测性指令流中检测存储排他操作，随后进行存储器障碍操作。处理器可以融合存储专有操作和存储器屏障操作，创建融合操作。可以传输和全局排序融合操作，并且响应于融合操作，处理器可以完成存储排他操作和存储器屏障操作两者。当融合操作通过处理器和一个或多个其它组件（例如高速缓存层级中的高速缓存）进行到系统中的订购点时，融合操作可以推动先前的存储器操作来实现存储器屏障操作。在一些实施例中，如果存储排他操作在订购点成功，则可以减少完成存储排他操作和后续数据存储器屏障操作的等待时间。

35. 发明授权

US07962730B2 Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler 有权
标题翻译：重新分配内存操作，分配一个加载/存储缓冲区条目，由存储操作占用，处理超出异常报告阶段，并从调度程序中退出
公开(公告)号：US07962730B2
公开(公告)日：2011-06-14
申请号：US12323266
申请日：2008-11-25
申请人： Wei-Han Lien , Po-Yung Chang
发明人： Wei-Han Lien , Po-Yung Chang
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
摘要： In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
摘要翻译：在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。

36. 发明授权

US08892841B2 Store handling in a processor 有权
标题翻译：在处理器中存储处理
公开(公告)号：US08892841B2
公开(公告)日：2014-11-18
申请号：US13544492
申请日：2012-07-09
申请人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
发明人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0833 , G06F9/3867 , G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
摘要翻译：在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

37. 发明申请

US20120278685A1 Store Handling in a Processor 有权
标题翻译：处理器中的商店处理
公开(公告)号：US20120278685A1
公开(公告)日：2012-11-01
申请号：US13544492
申请日：2012-07-09
申请人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
发明人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
IPC分类号： H03M13/05 , G06F11/10 , G06F12/08
CPC分类号： G06F12/0833 , G06F9/3867 , G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
摘要翻译：在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

38. 发明授权

US08239638B2 Store handling in a processor 有权
标题翻译：在处理器中存储处理
公开(公告)号：US08239638B2
公开(公告)日：2012-08-07
申请号：US11758303
申请日：2007-06-05
申请人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
发明人： Ramesh Gunna , Po-Yung Chang , Sudarshan Kadambi
IPC分类号： G06F11/08
CPC分类号： G06F12/0833 , G06F9/3867 , G06F12/0862 , G06F12/1045 , G06F2212/6028
摘要： In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
摘要翻译：在一个实施例中，处理器可以被配置为将ECC粒度存储写入数据高速缓存，而非ECC粒度存储可以与存储器请求缓冲器中的高速缓存数据合并。在一个实施例中，处理器可以被配置为检测受害者块回写命中存储器请求缓冲器中的一个或多个存储器（或反之亦然），并且可以将受害者块回写转换为填充。在一个实施例中，处理器可以推测性地发出来自加载/存储队列的负载后的存储，但是响应于负载上的窥探命中而阻止对存储的更新。

39. 发明授权

US07568087B2 Partial load/store forward prediction 有权
标题翻译：部分负载/存储正向预测
公开(公告)号：US07568087B2
公开(公告)日：2009-07-28
申请号：US12055016
申请日：2008-03-25
申请人： Sudarshan Kadambi , Po-Yung Chang , Eric Hao
发明人： Sudarshan Kadambi , Po-Yung Chang , Eric Hao
IPC分类号： G06F7/38 , G06F9/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/3826 , G06F9/3838
摘要： In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.
摘要翻译：在一个实施例中，处理器包括预测电路和耦合到预测电路的另一电路。预测电路被配置为预测在执行期间第一加载指令是否将经历部分存储以进行加载（PSTLF）事件。如果响应于执行期间的第一加载指令访问的多个字节包括至少响应于先前未提交的存储操作而更新的第一字节，并且还包括响应于先前未提交的存储器而不更新的至少第二字节，则发生PSTLF事件操作。耦合以接收第一加载指令，该电路被配置为响应于第一加载指令生成一个或多个加载操作。在处理器中执行加载操作以执行第一加载指令，并且多个加载操作取决于预测电路的预测。

40. 发明申请

US20090119488A1 Prefetch Unit 有权
标题翻译：预取单元
公开(公告)号：US20090119488A1
公开(公告)日：2009-05-07
申请号：US12350020
申请日：2009-01-07
申请人： Sudarshan Kadambi , Puneet Kumar , Po-Yung Chang
发明人： Sudarshan Kadambi , Puneet Kumar , Po-Yung Chang
IPC分类号： G06F9/06
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F2212/6028
摘要： In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.
摘要翻译：在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。预取单元被配置为同时维护多个单独的活动预取流。每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

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