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31. 发明申请

US20070235745A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070235745A1
公开(公告)日：2007-10-11
申请号：US11783577
申请日：2007-04-10
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L33/00 , H01L29/861 , H01L29/80
CPC分类号： H01L29/7808 , H01L29/0619 , H01L29/1608 , H01L29/165 , H01L29/6606 , H01L29/7802 , H01L29/7811 , H01L29/7828 , H01L29/8083 , H01L29/861 , H01L29/8618 , H01L29/872
摘要： Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.
摘要翻译：设定第二半导体区域的杂质浓度，使得当将预定的反向偏压施加到由第一半导体区域和第二半导体区域构成的异质结二极管时，至少在异种结区以外的击穿电压异质结二极管是半导体器件的击穿电压。

32. 发明申请

US20070210330A1 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070210330A1
公开(公告)日：2007-09-13
申请号：US11714214
申请日：2007-03-06
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/732 , H01L21/8234
CPC分类号： H01L29/267 , H01L21/0475 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.
摘要翻译：一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

33. 发明授权

US07071536B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US07071536B2
公开(公告)日：2006-07-04
申请号：US10772283
申请日：2004-02-06
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L27/082
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).

34. 发明授权

US06737677B2 Wide bandgap semiconductor device and method for manufacturing the same 有权
标题翻译：宽带隙半导体器件及其制造方法
公开(公告)号：US06737677B2
公开(公告)日：2004-05-18
申请号：US10410188
申请日：2003-04-10
申请人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi
发明人： Yoshio Shimoida , Saichirou Kaneko , Hideaki Tanaka , Masakatsu Hoshi
IPC分类号： H01L310312
CPC分类号： H01L29/66068 , H01L21/0465 , H01L21/049 , H01L21/8213 , H01L27/0605
摘要： The present invention provides a wide bandgap semiconductor device encompassing: (a) a drift layer of a first conductivity type made of a wide bandgap semiconductor material; (b) a body region of a second conductivity type made of the wide bandgap semiconductor material, disposed at the top surface of and in the drift layer; (c) a source region of the first conductivity type disposed in the body region; (d) a channel layer of the first conductivity type, disposed in the body region neighboring to the source region and further disposed in the drift layer; and (e) a gate electrode including semiconductor layer at the bottom so that the semiconductor layer directly contact with the top surface of the channel layer, the semiconductor layer made of a semiconductor material having a different bandgap energy from that of the wide bandgap semiconductor material.
摘要翻译：本发明提供一种宽带隙半导体器件，其包括：（a）由宽带隙半导体材料制成的第一导电类型的漂移层; （b）由宽带隙半导体材料制成的第二导电类型的体区，设置在漂移层的顶表面上; （c）设置在身体区域中的第一导电类型的源极区域; （d）第一导电类型的沟道层，设置在与源极区相邻的体区中，并且还设置在漂移层中; 和（e）在底部包括半导体层的栅电极，使得半导体层与沟道层的顶表面直接接触，由具有与宽带隙半导体材料的能隙不同的带隙能量的半导体材料制成的半导体层。

35. 发明授权

US09048103B2 Method for producing semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09048103B2
公开(公告)日：2015-06-02
申请号：US11988305
申请日：2006-06-26
申请人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号： H01L21/336 , H01L21/3105 , H01L29/78 , H01L21/04 , H01L29/267 , H01L29/66 , H01L29/16 , H01L29/772
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译：公开了一种用于制造半导体器件（20）的方法。半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A）所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。该方法包括以下顺序操作：i）形成栅绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。

36. 发明授权

US08053320B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08053320B2
公开(公告)日：2011-11-08
申请号：US11654666
申请日：2007-01-18
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L21/336
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

37. 发明授权

US07768035B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07768035B2
公开(公告)日：2010-08-03
申请号：US12066145
申请日：2006-08-02
申请人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/0328
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译：半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。异质半导体区域具有与半导体基底不同的带隙。异质半导体区域包括第一异质半导体区域和第二异质半导体区域。在形成栅极绝缘膜之前形成第一异质半导体区域。在形成栅极绝缘膜之后形成第二异质半导体区域。

38. 发明授权

US07749845B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07749845B2
公开(公告)日：2010-07-06
申请号：US11988944
申请日：2006-06-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
IPC分类号： H01L21/336
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译：一种制造具有多晶硅层（5）的半导体器件的方法包括：在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

39. 发明申请

US20090200575A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090200575A1
公开(公告)日：2009-08-13
申请号：US12423207
申请日：2009-04-14
申请人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译：半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及层之间的交叉点。半导体层各自含有第一导电类型的杂质。栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。源电极耦合到半导体区域。漏电极耦合到半导体衬底。

40. 发明授权

US07521731B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07521731B2
公开(公告)日：2009-04-21
申请号：US11444433
申请日：2006-06-01
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0328
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7813 , H01L29/8083
摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.
摘要翻译：本发明的半导体器件包括：第一导电型半导体基底; 以及切换机构，其形成在所述半导体基板的第一主面上并切换电流的开/关。在半导体基板中，多个柱状异质半导体区域在半导体衬底内隔开间隔地形成，并且异质半导体区域由与半导体衬底具有不同带隙的半导体材料制成，并且在第一主表面和与第一主表面相对的第二主表面。

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