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31. 发明专利

JPH08204161A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH08204161A
公开(公告)日：1996-08-09
申请号：JP1373895
申请日：1995-01-31
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , MIYANO SHINJI , SATO KATSUHIKO , NUMATA KENJI
IPC分类号： G11C11/401 , G11C11/00 , G11C11/4074 , G11C29/14 , H01L21/82 , H01L27/02 , H01L27/10 , H01L27/118
摘要： PURPOSE: To provide a semiconductor storage device of a memory macro system which can realize arbitrary storage capacity in a short design term, and reduce the chip cost without necessitating a large area on a semiconductor chip. CONSTITUTION: The semiconductor storage device is povided with submemory- macros 11, 12 having a DRAM memory cell array 21 and a row decoder 24 and a column decoder 27 which select an arbitrary memory cell out of the memory cell array, and a control part macro 15 having a DC potential generating circuit 32 which generates various kinds of DC potentials which are necessary at the time of operating the submemory-macros. A memory having the total storage capacity equal to arbitrary positive number times N-bit is constituted of one chip by combining at least one submemory-macro and one control part macro.

32. 发明专利

JPH08138376A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08138376A
公开(公告)日：1996-05-31
申请号：JP27750994
申请日：1994-11-11
申请人： TOSHIBA CORP
发明人： HAGA AKIRA , YABE TOMOAKI , MIYANO SHINJI , NUMATA KENJI
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4091 , G11C11/4094 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To obtain a semiconductor memory in which the possibility of erroneous function is reduced for a sense amplifier. CONSTITUTION: The semiconductor memory comprises a pair of bit lines BL, BBL, an equalizer circuit 4, a sense amplifier 6, a row system control circuit 5, and a sense amplifier drive circuit 7. The control circuit 5 controls the equalizer circuit 4 and a precharger in the drive circuit 7 independently. Continuous supply of precharge potential from the precharger to a pair of drive signal lines SAP, BSAN is interrupted immediately before a driver in the drive circuit 7 supplies a drive signal to the pair of drive signal lines SAP, BSAN. With such structure, potential of the pair of drive signal lines SAP, BSAN is not stabilized even if an activation signal for sense amplifier is outputted with a time lag behind an equalization signal and the possibility of erroneous function is lowered for the sense amplifier.

33. 发明专利

JPH07169261A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH07169261A
公开(公告)日：1995-07-04
申请号：JP31017593
申请日：1993-12-10
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , SATO KATSUHIKO , MIYANO SHINJI
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To realize a semiconductor memory device provided with a D type data latch circuit without remarkably increasing a chip size of a DRAM. CONSTITUTION:A load 23 is provided with N channel FETs N7, N8 between a VCC node and input/output line pair of a data bus side of a column selection gate 18 and adds a load control signal LDE to the gates. The D type latch circuit 16a whose respective gates of N channel FETs N3, N4 are connected intersecting each other to mutual drains, and whose sources are connected to a VSS. In such a constitution, since the data latch circuit 16a uses the same conductive type MOSFETs N3, N4, and does not use other conductive FETs, these separation areas are eliminated. Further, since the N3, N4 are simply constituted of alternately connection, the chip size is not remarkably increased. Further, in the case of refreshing latch data, when gate potential of N1, N2 for transfer gate is controlled to be higher than the VCC, for example, so as to boost to VCC+VTN1 by an internal control signal generation circuit, the node of higher level side between nodes D and /D becomes the VCC, and a write margin is increased.

34. 发明专利

JPH07161190A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH07161190A
公开(公告)日：1995-06-23
申请号：JP30372593
申请日：1993-12-03
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , SATOU KOUICHI
IPC分类号： G11C11/413 , G11C11/408 , H03K19/0948
摘要： PURPOSE:To accelerate a speed and to reduce power consumption of a CMOS type semiconductor IC circuit. CONSTITUTION:An address input buffer P0 has NOR gates 31-33, and inverters 34-39, receives an address input A0, and selectively outputs a signal A'0 having the same phase as the address A0 and a signal A'0 having reverse phase to a signal line group 31 at the time of chip enabling. A buffer P1 similarly selectively outputs A'1/A'1. The signal A'1/A'0 is input from the group to a two-input NAND gate S0, to a CMOS gate. Gates S1-S3 are similarly operated. PM0Ses P1, P2, NMOSes N1, N2 have threshold voltages. With the configuration, a leakage current of the CMOS gate is reduced by turning OFF a CMOS gate of next state which inputs a complementary signal group of outputs of an input buffer (Vth of the NMOS is deep and Vth of the PMOS is shallow) by the NMOSFET at the time of chip disabling except the time of chip enabling, thereby reducing current consumption at the time of the chip disabling.

35. 发明专利

JP2002217374A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002217374A
公开(公告)日：2002-08-02
申请号：JP2001010243
申请日：2001-01-18
申请人： TOSHIBA CORP
发明人： OTSUKA NOBUAKI , YABE TOMOAKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/08 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To reduce an layout area without deteriorating current capacity, in an ESD protective circuit for protecting a semiconductor element from electrostatic breakdown. SOLUTION: For example, when the ESD protective circuit 15 for protecting an internal circuit 13 from electrostatic breakdown is constituted by connecting a plurality of diodes 15a, 15b, 15c in cascade and pulling out a current in a forward direction, in a semiconductor device manufactured by CMOS process, the diodes 15a, 15b, 15c in each stage are formed by different sizes. More concretely, the diodes 15a, 15b, 15c of each stage are so constituted that the size is smaller gradually from an I/O pin 11 side toward a reference potential side (15a>15b>15c).

36. 发明专利

JPH10241361A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10241361A
公开(公告)日：1998-09-11
申请号：JP4068497
申请日：1997-02-25
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI
IPC分类号： G11C11/413 , G11C8/08 , G11C11/407 , G11C11/408
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory which is capable of reducing a chip size and also is capable of reducing the power consumption at the time of a standby and is capable of reducing a manufacturing cost. SOLUTION: A first discharge path 28 releasing a current to a power source potential Vss and a second discharge path 27 releasing the current to a negative potential Vbb are provided in parallel as the discharge path of a word line WL in a word line driver circuit. Here, at the non-selection time of the work line WL, the most part of discharge electric charges are made to be released to the power source Vss by activating the first discharge path 28 and thereafter, the word line is made to be pulled down to the negative potential Vbb by activating the second discharge path 27. Consequently since a discharging current flowing into a Vbb generating circuit can be reduced, the word line can be discharged with a Vbb generating circuit whose current driving ability is small. Thus, the chip size of the semiconductor memory is reduced and also the power consumption at the time of the standby is reduced and the manufacturing cost is also reduced.

37. 发明专利

JPH10241359A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10241359A
公开(公告)日：1998-09-11
申请号：JP3763097
申请日：1997-02-21
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C11/4096
摘要： PROBLEM TO BE SOLVED: To provide a clock synchronization type DRAM capable of reducing the power consumption of a chip by making charging and discharging currents of a DG line pair small. SOLUTION: This memory is made so as to control the precharge and the equalization of the DG line pair by providing a column address change detecting circuit 53 in the overlaid DG type DRAM of a clock synchronization type. Here, the memory is made so as to precharge and equalize the DG lines only when only an LSB is changed and other column bits are not changed by setting an address selecting the DG line multiplexer of the front stage of a DG buffer 22 in the LSB of a column address and by detecting the column address change in the first stage of the pipe line of a column access path. Thus, the charging and discharging currents of the DG line pair are made to be reduced by saving the spurious precharge of the DG line pair, the power consumption of the chip is reduced.

38. 发明专利

JPH08139290A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08139290A
公开(公告)日：1996-05-31
申请号：JP27751194
申请日：1994-11-11
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , MIYANO SHINJI , NUMATA KENJI
IPC分类号： G11C11/401 , G11C7/06 , G11C7/10 , G11C8/12 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108
摘要： PURPOSE: To provide a semiconductor memory in which the inversion of the data of a column not transferred can be prevented even when the number of the columns to be simultaneously transferred is large. CONSTITUTION: The semiconductor memory comprises a memory cell array 1, a sense amplifier group provided at each column, a driver precharger for activating the group, a data latch circuit group 3 provided at each column to temporarily store the data supplied from a DQ bus 20, and a transfer gate group 4 for simultaneously transferring the data stored in the group 3 to the amplifier group. The array 1 is divided into a plurality of blocks B1, B2 including desired number of columns, and the precharger is divided to a plurality of circuits 5-1 to 5-3 at the respective blocks B1, B2.

39. 发明专利

JPH07312084A CACHE MEMORY INCORPORATED MEMORY DEVICE 失效
公开(公告)号：JPH07312084A
公开(公告)日：1995-11-28
申请号：JP10388294
申请日：1994-05-18
申请人： TOSHIBA CORP
发明人： SATO KATSUHIKO , MIYANO SHINJI , YABE TOMOAKI , FURUYAMA TORU
IPC分类号： G11C11/409 , G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/407
摘要： PURPOSE:To realize high speed writing for a cache memory. CONSTITUTION:A initializing circuit 21 for a pair of data line is connected to a pair of data line DL, /DL. The initializing circuit 21 makes the pair of data line DL, /DL the same potential by short-circuiting or pre-charging. The initializing circuit 21 is controlled by an initialization control circuit 24. A first transfer gate 12 or a second transfer gate 13 is opened after short circuit or pre-charge of the pair of data line DL, /DL is finished, and data is written in a cache memory 11. The first transfer gate 12 is controlled by a control circuit 22, and the second transfer gate 13 is controlled by a column decoder (control circuit) 24.

40. 发明专利

JPH07287981A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH07287981A
公开(公告)日：1995-10-31
申请号：JP8145594
申请日：1994-04-20
申请人： TOSHIBA CORP
发明人： YABE TOMOAKI , NUMATA KENJI
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/401 , G11C11/409
摘要： PURPOSE:To secure reliability of a gate insulation film for a long time and to reduce the cost of a screening test for the gate insulation film by making duty with which word line boosting potential is applied to a gate insulation film of a MOS transistor for transferring electric charges of a memory cell connected to a word line smaller than conventional duty in a DRAM provided with data latch. CONSTITUTION:This memory has a data latch circuit 16 provided at the next stage of a sense amplifier 14 sensing data read out from a DRAM cell array 10 through a transfer gate 15, and data transfer is performed between a data latch circuit and a data bus DQ, the inverse of DQ. The DRAM provided with data latch circuit is provided with a row system control circuit 23c controlling the time for setting the word line selected by a row decoder 12 in an active state to a fixed time or less.

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