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31. 发明申请

US20050196878A1 Single-phase c-axis doped PGO ferroelectric thin films 有权
标题翻译：单相c轴掺杂PGO铁电薄膜
公开(公告)号：US20050196878A1
公开(公告)日：2005-09-08
申请号：US11046620
申请日：2005-01-28
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/316 , H01L41/22
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby−xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

32. 发明申请

US20050052942A1 Trench isolated cross-point memory array 有权
公开(公告)号：US20050052942A1
公开(公告)日：2005-03-10
申请号：US10971203
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , G11C8/02
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

33. 发明申请

US20050009286A1 Method of fabricating nano-scale resistance cross-point memory array 有权
标题翻译：制造纳米级电阻交叉点存储阵列的方法
公开(公告)号：US20050009286A1
公开(公告)日：2005-01-13
申请号：US10909218
申请日：2004-07-29
申请人： Sheng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L27/105 , G11C13/00 , H01L21/8246 , H01L27/115 , H01L27/24 , H01L43/08 , H01L27/108
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

34. 发明申请

US20070272960A1 Ferroelectric memory transistor with conductive oxide gate structure 审中-公开
标题翻译：具有导电氧化物栅极结构的铁电存储晶体管
公开(公告)号：US20070272960A1
公开(公告)日：2007-11-29
申请号：US11890692
申请日：2007-08-07
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L29/76
CPC分类号： G11C11/22 , H01L29/40111 , H01L29/40114 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

35. 发明申请

US20060180816A1 Wide wavelength range silicon electroluminescence device 审中-公开
标题翻译：宽波长范围的硅电致发光器件
公开(公告)号：US20060180816A1
公开(公告)日：2006-08-17
申请号：US11058505
申请日：2005-02-14
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
IPC分类号： H01L29/26
CPC分类号： H05B33/145
摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.
摘要翻译：提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。通常，SRSO的Si浓度范围为5〜40％。在一个方面，使用DC溅射工艺形成SRSO层。另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

36. 发明申请

US20060160335A1 Rare earth element-doped silicon/silicon dioxide lattice structure 失效
标题翻译：稀土元素掺杂硅/二氧化硅晶格结构
公开(公告)号：US20060160335A1
公开(公告)日：2006-07-20
申请号：US11039463
申请日：2005-01-19
申请人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
发明人： Tingkai Li , Wei Gao , Yoshi Ono , Sheng Hsu
IPC分类号： H01L21/20
CPC分类号： C23C14/16 , C03C17/34 , C23C14/10 , C23C28/322 , C23C28/323 , C23C28/345 , C23C28/3455 , C23C28/42 , H01L21/02164 , H01L21/02266 , H01L21/0237 , H01L21/02532 , H01L21/02573 , H01L21/0259 , H01L21/02631 , H01L21/02667 , H01L21/31608 , H01L33/26
摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.
摘要翻译：提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。一方面，稀土元素和Si共溅射。通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

37. 发明申请

US20060038242A1 Semiconductive metal oxide thin film ferroelectric memory transistor 有权
标题翻译：半导体金属氧化物薄膜铁电存储晶体管
公开(公告)号：US20060038242A1
公开(公告)日：2006-02-23
申请号：US10922712
申请日：2004-08-20
申请人： Sheng Hsu , Tingkai Li , Jong-Jan Lee
发明人： Sheng Hsu , Tingkai Li , Jong-Jan Lee
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/7869 , H01L29/516 , H01L29/66545 , H01L29/66553 , H01L29/78621
摘要： The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.
摘要翻译：本发明公开了一种采用半导体金属氧化物作为晶体管导电通道的新型晶体管结构。通过用半导体金属氧化物沟道代替硅导电通道，晶体管可以实现更简单的制造工艺，并且可以实现3D结构以增加电路密度。所公开的半导体金属氧化物晶体管可以在铁电非易失性存储器件中具有很大的潜力，具有与铁电材料良好的界面性质，与铁电层的可能的晶格匹配，减少或消除氧扩散问题以提高可靠性的另外的优点铁电存储晶体管。半导体金属氧化物膜优选是在晶体管工作条件下表现出半导体性质的金属氧化物，例如在二氧化铈或RuO 2 。本发明的铁电晶体管可以是金属铁电半导体金属氧化物FET，其具有设置在设置在基板上的半导体金属氧化物沟道上的铁电层上的顶部金属电极的栅极堆叠。使用附加的底部电极和栅极电介质层，本发明的铁电晶体管也可以是金属 - 铁电 - 金属（可选） - 门电介质（可选） - 导电金属氧化物FET。

38. 发明申请

US20060035390A1 Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides 失效
公开(公告)号：US20060035390A1
公开(公告)日：2006-02-16
申请号：US11249883
申请日：2005-10-12
申请人： Tingkai Li , Sheng Hsu
发明人： Tingkai Li , Sheng Hsu
IPC分类号： H01L21/469
CPC分类号： H01L21/28273 , C23C16/0272 , C23C16/40 , C23C16/56 , H01L21/28194 , H01L21/28291 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517
摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

39. 发明申请

US20050054166A1 Conductive metal oxide gate ferroelectric memory transistor 失效
标题翻译：导电金属氧化物栅极铁电存储晶体管
公开(公告)号：US20050054166A1
公开(公告)日：2005-03-10
申请号：US10659547
申请日：2003-09-09
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L27/105 , G11C11/22 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L29/78
CPC分类号： G11C11/22 , H01L21/28273 , H01L21/28291 , H01L29/66545 , H01L29/66553 , H01L29/66825 , H01L29/6684 , H01L29/78391
摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.
摘要翻译：本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

40. 发明申请

US20070108502A1 Nanocrystal silicon quantum dot memory device 审中-公开
标题翻译：纳米晶硅量子点存储器件
公开(公告)号：US20070108502A1
公开(公告)日：2007-05-17
申请号：US11281955
申请日：2005-11-17
申请人： Tingkai Li , Sheng Hsu , Lisa Stecker
发明人： Tingkai Li , Sheng Hsu , Lisa Stecker
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/349 , G11C16/3495 , G11C2216/08 , H01L29/15 , H01L29/40114 , H01L29/42324 , H01L29/4925 , H01L29/66825
摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).
摘要翻译：已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

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