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31. 发明授权

US08136084B2 Arranging through silicon vias in IC layout 有权
标题翻译：在IC布局中排列硅通孔
公开(公告)号：US08136084B2
公开(公告)日：2012-03-13
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G06F17/52
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

32. 发明申请

US20110180896A1 METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
标题翻译：用氧化铝/氮化物层生产粘结的结构的方法
公开(公告)号：US20110180896A1
公开(公告)日：2011-07-28
申请号：US12692983
申请日：2010-01-25
申请人： Gerd Pfeiffer , Haizhou Yin , Edmund J. Sprogis , Subramanian Iyer , Zhibin Ren , Dae-Gyu Park , Oleg Gluschenkov
发明人： Gerd Pfeiffer , Haizhou Yin , Edmund J. Sprogis , Subramanian Iyer , Zhibin Ren , Dae-Gyu Park , Oleg Gluschenkov
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76256
摘要： A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.
摘要翻译：形成接合晶片结构的方法包括：在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。或者，可以在接合之前在氮化硅层上形成第三氧化硅层。然后在第一和第三氧化硅层之间形成键合界面。还提供了通过这种方法形成的接合晶片结构。

33. 发明申请

US20110177435A1 Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
标题翻译：具有亚光刻特征以防止不期望的晶片图案化的光掩模
公开(公告)号：US20110177435A1
公开(公告)日：2011-07-21
申请号：US12690312
申请日：2010-01-20
申请人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/42 , G03F1/36 , G03F1/38
摘要： A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.
摘要翻译：在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

34. 发明授权

US07964967B2 High surface area aluminum bond pad for through-wafer connections to an electronic package 有权
标题翻译：高表面积铝合金焊盘，用于通过晶片连接到电子封装
公开(公告)号：US07964967B2
公开(公告)日：2011-06-21
申请号：US12046737
申请日：2008-03-12
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

35. 发明申请

US20110057319A1 ARRANGING THROUGH SILICON VIAS IN IC LAYOUT 有权
标题翻译：通过IC布局中的硅胶排列
公开(公告)号：US20110057319A1
公开(公告)日：2011-03-10
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, JR. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F17/50
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

36. 发明申请

US20100155936A1 METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：稀释半导体基板的方法
公开(公告)号：US20100155936A1
公开(公告)日：2010-06-24
申请号：US12342393
申请日：2008-12-23
申请人： Steven R. Codding , Timothy C. Krywanczyk , Timothy E. Neary , Edmund J. Sprogis
发明人： Steven R. Codding , Timothy C. Krywanczyk , Timothy E. Neary , Edmund J. Sprogis
IPC分类号： H01L21/30 , H01L23/488
CPC分类号： H01L21/6835 , H01L21/6836 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/27436 , H01L2224/83191 , H01L2924/00014 , H01L2924/01057 , H01L2924/09701 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.
摘要翻译：在半导体基板的正面上形成C4研磨胶带和激光烧蚀粘合剂层。然后将载体基板连接到激光烧蚀粘合剂层。通过抛光或研磨使半导体衬底的背面变薄，在此期间，载体衬底提供机械支撑以使半导体衬底的薄化能够达到约25μm的厚度。胶片框架胶带附着到减薄的半导体衬底的背面，激光烧蚀粘合剂层通过激光烧蚀，从而使载体衬底与C4研磨胶带的背面分离。薄膜框架胶带，变薄的半导体衬底和C4研磨胶带的组装被切割。通过紫外线照射C4研磨胶带以变得粘合性变差，随后被除去。

37. 发明授权

US07719118B2 Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package 有权
标题翻译：将与基板电连接的通孔和与基板隔离的其它通孔的半导体芯片级封装以及形成封装的方法
公开(公告)号：US07719118B2
公开(公告)日：2010-05-18
申请号：US11838917
申请日：2007-08-15
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Edmund J. Sprogis
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3157 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/82 , H01L2224/0401 , H01L2224/16 , H01L2924/10253 , H01L2924/12043 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.
摘要翻译：形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的方法。

38. 发明授权

US07683478B2 Hermetic seal and reliable bonding structures for 3D applications 失效
标题翻译：密封密封和3D应用的可靠结合结构
公开(公告)号：US07683478B2
公开(公告)日：2010-03-23
申请号：US12026776
申请日：2008-02-06
申请人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
发明人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/34
CPC分类号： H01L25/50 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
摘要翻译：一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

39. 发明申请

US20100019346A1 IC HAVING FLIP CHIP PASSIVE ELEMENT AND DESIGN STRUCTURE 审中-公开
标题翻译： IC具有FLIP芯片被动元件和设计结构
公开(公告)号：US20100019346A1
公开(公告)日：2010-01-28
申请号：US12180810
申请日：2008-07-28
申请人： Mete Erturk , Edmund J. Sprogis , Anthony K. Stamper
发明人： Mete Erturk , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L24/91 , H01F17/0006 , H01F27/027 , H01L23/645 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/94 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48463 , H01L2224/73257 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30105 , H01L2224/05599 , H01L2924/013 , H01L2924/00013 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： IC and design structure including various ways of raising a passive element such as an inductor off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.
摘要翻译：提出了IC和设计结构，其中包括从基板表面起提高无源元件（如电感器）以提高无源元件的性能的各种方式。可以提供第一晶片，并且从第二晶片切割无源元件。无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。

40. 发明申请

US20090206407A1 SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING 有权
标题翻译：具有拉伸和/或压缩应力的半导体器件及其制造方法
公开(公告)号：US20090206407A1
公开(公告)日：2009-08-20
申请号：US12033280
申请日：2008-02-19
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
IPC分类号： H01L29/78 , H01L21/762
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译：公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。第一氧化沟槽在通道中产生应变分量以增加器件性能。

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