专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5397723A Process for forming arrayed field effect transistors highly integrated on substrate 失效
标题翻译：用于形成高度集成在衬底上的阵列场效应晶体管的工艺
公开(公告)号：US5397723A
公开(公告)日：1995-03-14
申请号：US728585
申请日：1991-07-11
申请人： Riichiro Shirota , Masaki Momodomi , Ryozo Nakayama , Seiichi Aritome , Ryouhei Kirisawa , Tetsuro Endoh , Shigeyoshi Watanabe
发明人： Riichiro Shirota , Masaki Momodomi , Ryozo Nakayama , Seiichi Aritome , Ryouhei Kirisawa , Tetsuro Endoh , Shigeyoshi Watanabe
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265 , H01L21/465
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11517
摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.
摘要翻译：用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二绝缘层。蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

32. 发明授权

US4733374A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4733374A
公开(公告)日：1988-03-22
申请号：US844626
申请日：1986-03-27
申请人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
发明人： Tohru Furuyama , Shigeyoshi Watanabe , Tatsuo Ikawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/408 , G11C11/4097 , G11C7/00
CPC分类号： G11C8/14 , G11C11/408 , G11C11/4097
摘要： A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.
摘要翻译：半导体存储器件具有N个读出放大器，每个读出放大器具有第一和第二输入端，N个第一存储单元，N个第二存储器单元，N个第一位线，每个第一位线连接到同一列的第一存储器单元并连接到第一输入端一个读出放大器的一个端子，以及N个第二位线，每个第二位线连接到同一列的第二存储器单元并连接到一个读出放大器的第二输入端。第一存储器单元形成在第一存储单元区域中，并且第二存储器单元形成在与第一存储单元区域相邻布置的第二存储器单元区域中，并且与第一存储器单元区域相对于读出放大器。

33. 发明授权

US4494219A Nonvolatile read only memory device 失效
标题翻译：非易失性只读存储器件
公开(公告)号：US4494219A
公开(公告)日：1985-01-15
申请号：US344050
申请日：1982-01-29
申请人： Sumio Tanaka , Shigeyoshi Watanabe
发明人： Sumio Tanaka , Shigeyoshi Watanabe
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , G11C16/32 , G11C29/00 , G11C29/12 , G11C29/24 , G11C7/00
CPC分类号： G11C16/32 , G11C16/28
摘要： A nonvolatile read only memory detects a time varying change of the amount of data written in the memory cell transistor using a circuit for supplying a constant potential which is higher than the threshold voltage of a reference cell transistor and which is independent of a power source voltage used for reading out connected to the gate of the reference cell transistor.
摘要翻译：非易失性只读存储器使用用于提供高于参考单元晶体管的阈值电压的恒定电位的电路来检测写入存储单元晶体管的数据量的时变变化，并且其独立于电源电压用于读出连接到参考单元晶体管的栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式