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31. 发明申请

US20070200138A1 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US20070200138A1
公开(公告)日：2007-08-30
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译：半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

32. 发明授权

US4896199A Semiconductor device with protective means against overheating 失效
标题翻译：具有防止过热的保护装置的半导体器件
公开(公告)号：US4896199A
公开(公告)日：1990-01-23
申请号：US169001
申请日：1988-03-16
申请人： Yukio Tsuzuki , Masami Yamaoka
发明人： Yukio Tsuzuki , Masami Yamaoka
IPC分类号： H01L23/58 , H01L21/822 , H01L23/34 , H01L27/02 , H01L27/04 , H01L29/78
CPC分类号： H01L29/7803 , H01L23/34 , H01L27/0248 , H01L29/7804 , H01L29/7808 , H01L2924/0002
摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

33. 发明授权

US4760434A Semiconductor device with protective means against overheating 失效
标题翻译：具有防止过热的保护装置的半导体器件
公开(公告)号：US4760434A
公开(公告)日：1988-07-26
申请号：US935718
申请日：1986-11-28
申请人： Yukio Tsuzuki , Masami Yamaoka
发明人： Yukio Tsuzuki , Masami Yamaoka
IPC分类号： H01L23/58 , H01L21/822 , H01L23/34 , H01L27/02 , H01L27/04 , H01L29/78 , G05F1/40 , H01L23/56 , H01L31/00
CPC分类号： H01L29/7803 , H01L23/34 , H01L27/0248 , H01L29/7804 , H01L29/7808 , H01L2924/0002
摘要： A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.
摘要翻译：半导体衬底具有功率区域和控制区域。控制区域位于基板的中心部分，功率区域围绕控制区域并与之分离。在功率区域上形成垂直型MOS晶体管即有源半导体元件。在控制区域的一部分上形成绝缘膜。在绝缘膜上形成用作热敏元件的多晶硅二极管。在控制区域上还形成有包括横向型MOS晶体管的控制部。横向型MOS晶体管被连接以从多晶硅二极管接收信号。此外，在绝缘膜上形成确定电路常数的多晶硅电阻器。 MOS晶体管响应于来自热敏元件的信号保护有源半导体元件，表明半导体衬底的温度已经升高到预定值以上。例如，可以禁用活性半导体元件，直到检测到的温度下降到预定值以下。

34. 发明授权

US4680608A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4680608A
公开(公告)日：1987-07-14
申请号：US697571
申请日：1985-02-01
申请人： Yukio Tsuzuki , Masami Yamaoka , Shoji Toyoshima
发明人： Yukio Tsuzuki , Masami Yamaoka , Shoji Toyoshima
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/732 , H01L29/72
CPC分类号： H01L29/0813
摘要： This application describes a semiconductor device having a power amplifier pattern consisting of a plurality of parallel-connected transistor unit cells with emitters thereof being arrayed like meshes, wherein the width of the emitter of each transistor unit cell is not in excess of 50 microns. The limitation of the emitter width contributes to enhancement of the reverse-bias breakdown endurance.
摘要翻译：本申请描述了一种具有功率放大器模式的半导体器件，该功率放大器模式由多个并联的晶体管单元电池组成，其发射极像网格一样排列，其中每个晶体管单电池的发射极的宽度不超过50微米。发射极宽度的限制有助于提高反向偏压击穿耐力。

35. 发明授权

US09099387B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09099387B2
公开(公告)日：2015-08-04
申请号：US13171115
申请日：2011-06-28
申请人： Yukio Tsuzuki , Makoto Asai
发明人： Yukio Tsuzuki , Makoto Asai
IPC分类号： H01L29/66 , H01L29/06 , H01L21/265 , H01L29/10 , H01L29/417 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7806
摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.
摘要翻译：半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，以p导电型布置的主侧n导电型区域层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

36. 发明授权

US08841699B2 Semiconductor device including insulated gate bipolar transistor and diode 有权
标题翻译：半导体器件包括绝缘栅双极晶体管和二极管
公开(公告)号：US08841699B2
公开(公告)日：2014-09-23
申请号：US13495051
申请日：2012-06-13
申请人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
发明人： Yukio Tsuzuki , Hiromitsu Tanabe , Kenji Kouno
IPC分类号： H01L29/04 , H01L29/10 , H01L29/66 , H01L29/739 , H01L29/861 , H01L29/32 , H01L21/263
CPC分类号： H01L21/263 , H01L29/1095 , H01L29/32 , H01L29/7397 , H01L29/861
摘要： A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region.
摘要翻译：半导体器件包括IGBT形成区域和二极管形成区域。 IGBT形成区域包括作为IGBT工作的IGBT工作部和不作为IGBT工作的稀疏部。 IGBT操作部分包括沟道区，并且所述稀疏部包括第一阳极区。二极管形成区域包括第二阳极区域。当区域密度定义为通过在深度方向上积分沟道区域，第一阳极区域和第二阳极区域中的每一个中的第二导电类型杂质的浓度分布而计算出的值时，沟道区域的面积密度为高于第一阳极区域的面积密度和第二阳极区域的面积密度。

37. 发明授权

US08729600B2 Insulated gate bipolar transistor (IGBT) with hole stopper layer 有权
标题翻译：绝缘栅双极晶体管（IGBT），带有阻塞层
公开(公告)号：US08729600B2
公开(公告)日：2014-05-20
申请号：US13534530
申请日：2012-06-27
申请人： Yukio Tsuzuki , Kenji Kouno , Hiromitsu Tanabe
发明人： Yukio Tsuzuki , Kenji Kouno , Hiromitsu Tanabe
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/861
摘要： A semiconductor device has a first conductivity-type semiconductor substrate, second conductivity-type channel regions, and second conductivity-type thinning-out regions. The channel regions and the thinning-out regions are formed adjacent to a substrate surface of the semiconductor substrate. Further, a hole stopper layer is formed in each of the thinning-out regions to divide the thinning-out region into a first part adjacent to the substrate surface and a second part adjacent to a bottom of the thinning-out region. The hole stopper layer has an area density of equal to or less than 4.0×1012 cm−2 to permit a depletion layer to punch through the hole stopper layer, thereby to restrict breakdown properties from being decreased.
摘要翻译：半导体器件具有第一导电型半导体衬底，第二导电型沟道区和第二导电型稀疏区。沟道区域和稀疏区域形成为与半导体衬底的衬底表面相邻。此外，在每个稀疏区域中形成孔阻挡层，以将稀疏区域划分成与衬底表面相邻的第一部分和与稀疏区域的底部相邻的第二部分。该孔阻挡层的面积密度为4.0×10 12 cm -2以下，能够使耗尽层穿过该阻挡层，从而能够抑制击穿性的降低。

38. 发明授权

US08648385B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08648385B2
公开(公告)日：2014-02-11
申请号：US13301973
申请日：2011-11-22
申请人： Kenji Kouno , Hiromitsu Tanabe , Yukio Tsuzuki
发明人： Kenji Kouno , Hiromitsu Tanabe , Yukio Tsuzuki
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.
摘要翻译：半导体器件包括具有第一表面和第二表面的半导体衬底。半导体基板具有包括IGBT区域和位于IGBT区域附近的二极管区域的元件区域。在IGBT区域中形成IGBT元件。在二极管区域中形成二极管元件。第一导电类型的重掺杂区域位于围绕元件区域的第一表面侧上。第一导电类型的吸收区域位于元件区域周围的第二表面侧。第二导电类型的第三半导体区域位于元件区域周围的第二表面侧。

39. 发明授权

US08614483B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US08614483B2
公开(公告)日：2013-12-24
申请号：US13313050
申请日：2011-12-07
申请人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
发明人： Hiromitsu Tanabe , Yukio Tsuzuki , Kenji Kouno , Tomofusa Shiga
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/66348
摘要： An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.
摘要翻译：绝缘栅半导体器件包括第一导电型半导体衬底，在衬底的第一表面侧上的第二导电型基极层，将基极层分为沟道和浮动层的沟槽，以及第一导电型发射极区域其形成在沟道层中并与沟槽接触。半导体器件包括沟槽中的栅极绝缘层，绝缘层上的栅极电极，电连接到发射极区域和浮置层的发射极电极，衬底中的第二导电型集电极层，以及集电极电极集电极层。浮置层的杂质浓度低于沟道层。浮动层具有位于距离基板的第一表面预定深度并且至少部分地与绝缘层间隔开的第一导电型孔阻挡层。

40. 发明申请

US20110260212A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110260212A1
公开(公告)日：2011-10-27
申请号：US13090288
申请日：2011-04-20
申请人： Yukio Tsuzuki , Kenji Kouno
发明人： Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696
摘要： An insulated gate semiconductor device includes a semiconductor substrate, a drift layer on the substrate, a base layer on the drift layer, a ring-shaped gate trench dividing the base layer into a channel layer and a floating layer, an emitter region located in the channel layer to be in contact with a side surface of the gate trench, a well region located on the periphery of a cell area of the base layer and having a depth greater than a depth of the base layer, and a ring-shaped buffer trench located adjacent to and spaced from the gate trench in a length direction of the gate trench. An edge of the well region is located in an area enclosed by the buffer trench in the length direction of the gate trench.
摘要翻译：绝缘栅极半导体器件包括半导体衬底，衬底上的漂移层，漂移层上的基极层，将基极层划分成沟道层和浮动层的环形栅极沟槽，位于沟道层与栅极沟槽的侧表面接触，位于基底层的单元区域的周边上并且具有大于基底层的深度的深度的阱区，以及环形缓冲沟槽位于栅极沟槽的长度方向附近并与栅极沟槽间隔开。阱区域的边缘位于由栅极沟槽的长度方向上的缓冲沟槽包围的区域中。

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