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31. 发明申请

US20070228929A1 Display apparatus 审中-公开
标题翻译：显示装置
公开(公告)号：US20070228929A1
公开(公告)日：2007-10-04
申请号：US11657046
申请日：2007-01-24
申请人： Mutsumi Suzuki , Masakazu Sagawa , Toshiaki Kusunoki
发明人： Mutsumi Suzuki , Masakazu Sagawa , Toshiaki Kusunoki
IPC分类号： H01J1/00 , H01J1/62 , H01J19/06 , H01J63/04
CPC分类号： H01J31/127 , H01J29/04
摘要： In a matrix electron emitter display using a thin-film electron emitter, a required resistance value of a top electrode, which value is determined by voltage drop at the top electrode, is small, and selection of a material and film thickness of the top electrode have been limited. Use of cathode structure which improves the capability of feeding from a feeding line to a thin-film electron emitter element improves the electron emission efficiency, and permits achieving higher luminance and lower power of a display apparatus.
摘要翻译：在使用薄膜电子发射体的矩阵电子发射体显示器中，由顶部电极的电压降决定该值的顶部电极的所需电阻值小，并且选择上部电极的材料和膜厚度受到限制使用提高从馈电线向薄膜电子发射体元件供给的能力的阴极结构提高了电子发射效率，并且可以实现显示装置的更高的亮度和更低的功率。

32. 发明申请

US20060267480A1 Display device having a thin film electron source array 失效
公开(公告)号：US20060267480A1
公开(公告)日：2006-11-30
申请号：US11501745
申请日：2006-08-10
申请人： Toshiaki Kusunoki , Masakazu Sagawa , Mutsumi Suzuki
发明人： Toshiaki Kusunoki , Masakazu Sagawa , Mutsumi Suzuki
IPC分类号： H01J63/04
CPC分类号： H01J31/127 , B82Y10/00 , H01J1/312 , Y10S345/905
摘要： The invention provides a display device using thin film type electron sources having a structure that can be formed in a simple manufacturing process. A lower electrode, a protective insulating layer and an interlayer film are formed on a cathode substrate. An upper bus electrode made from a laminated film of a metal film lower layer and a metal film upper layer is provided further on the interlayer film. A film of an upper electrode of a thin film type electron source for each pixel constituted by an insulating layer serving as an electron accelerating layer on the lower electrode and the upper electrode is formed on two stripe electrodes of the upper bus electrode in that pixel and another upper bus electrode in an adjacent pixel by sputtering. Then, the upper electrode is separated by self-alignment due to a setback portion of the metal film lower layer and an appentice of the metal film upper layer of the corresponding upper bus electrode. Thus, a thin film type electron source separated in accordance with each pixel is formed.

33. 发明授权

US07129641B2 Display device having a thin film electron source array 有权
标题翻译：具有薄膜电子源阵列的显示装置
公开(公告)号：US07129641B2
公开(公告)日：2006-10-31
申请号：US10724149
申请日：2003-12-01
申请人： Toshiaki Kusunoki , Masakazu Sagawa , Mutsumi Suzuki
发明人： Toshiaki Kusunoki , Masakazu Sagawa , Mutsumi Suzuki
IPC分类号： G09G3/10
CPC分类号： H01J31/127 , B82Y10/00 , H01J1/312 , Y10S345/905
摘要： The invention provides a display device using thin film type electron sources having a structure that can be formed in a simple manufacturing process. A lower electrode, a protective insulating layer and an interlayer film are formed on a cathode substrate. An upper bus electrode made from a laminated film of a metal film lower layer and a metal film upper layer is provided further on the interlayer film. A film of an upper electrode of a thin film type electron source for each pixel constituted by an insulating layer serving as an electron accelerating layer on the lower electrode and the upper electrode is formed on two stripe electrodes of the upper bus electrode in that pixel and another upper bus electrode in an adjacent pixel by sputtering. Then, the upper electrode is separated by self-alignment due to a setback portion of the metal film lower layer and an appentice of the metal film upper layer of the corresponding upper bus electrode. Thus, a thin film type electron source separated in accordance with each pixel is formed.
摘要翻译：本发明提供一种使用薄膜型电子源的显示装置，其具有能够以简单的制造工艺形成的结构。在阴极基板上形成下电极，保护绝缘层和中间膜。在层间膜上还设置由金属膜下层和金属膜上层的叠层膜制成的上部总线电极。在该像素中的上部总线电极的两个条状电极上形成由用于在下部电极和上部电极上的电子加速层的绝缘层构成的每个像素的薄膜型电子源的上部电极的膜，通过溅射在相邻像素中的另一个上总线电极。然后，由于金属膜下层的后退部分和相应的上部总线电极的金属膜上层的附着，上部电极由于自对准而分离。因此，形成根据每个像素分离的薄膜型电子源。

34. 发明授权

US07116291B1 Image display and method of driving image display 失效
标题翻译：图像显示和驱动图像显示的方法
公开(公告)号：US07116291B1
公开(公告)日：2006-10-03
申请号：US10031377
申请日：2000-09-04
申请人： Mutsumi Suzuki , Toshiaki Kusunoki , Makoto Okai , Masakazu Sagawa , Akitoshi Ishizaka
发明人： Mutsumi Suzuki , Toshiaki Kusunoki , Makoto Okai , Masakazu Sagawa , Akitoshi Ishizaka
IPC分类号： G09G3/30
CPC分类号： G09G3/22 , H01J31/127
摘要： The present invention provides an image display capable of reducing power used up or consumed by a thin-film electron-emitter matrix. As a typical one, there is provided an image display which comprises a display device including a first plate which has a plurality of electron-emitter elements each having a structure comprised of a base electrode, an insulating layer and a top electrode stacked on one another in this order, the electron-emitter element emitting electrons from the surface of the top electrode when a voltage of positive polarity is applied to the top electrode; a plurality of first electrodes for respectively applying driving voltages to the base electrodes of the electron-emitter elements lying in a row direction, of the plurality of electron-emitter elements; and a plurality of second electrodes for respectively applying driving voltages to the top electrodes of the electron-emitter elements lying in a column direction, of the plurality of electron-emitter elements, a frame component, and a second plate having phosphors, wherein a space surrounded by the first plate, the frame component and the second plate is brought into vacuum. In the image display, the first electrode and/or the second electrode held in a non-selected state is set to a high-impedance state.
摘要翻译：本发明提供能够减少由薄膜电子发射器矩阵使用或消耗的功率的图像显示器。作为典型的图像显示器，提供了一种图像显示器，其包括显示装置，该显示装置包括第一板，该第一板具有多个电子发射元件，每个电子发射元件具有由彼此堆叠的基极，绝缘层和顶电极组成的结构按照该顺序，当正极性的电压施加到顶部电极时，从顶部电极的表面发射电子的电子 - 发射体元件; 多个第一电极，分别向多个电子发射元件的行方向的电子发射元件的基极施加驱动电压; 以及多个第二电极，用于分别向多个电子发射元件的列方向上的电子发射元件的顶部电极，框架部件和具有荧光体的第二板分别施加驱动电压，其中空间被第一板包围，框架部件和第二板被置于真空中。在图像显示中，保持在未选择状态的第一电极和/或第二电极被设置为高阻抗状态。

35. 发明授权

US07095169B2 Flat panel display device 有权
标题翻译：平板显示设备
公开(公告)号：US07095169B2
公开(公告)日：2006-08-22
申请号：US10682024
申请日：2003-10-10
申请人： Tetsu Ohishi , Masakazu Sagawa , Yoshie Kodera , Motoyuki Miyata , Akinori Maeda
发明人： Tetsu Ohishi , Masakazu Sagawa , Yoshie Kodera , Motoyuki Miyata , Akinori Maeda
IPC分类号： H01J63/04
CPC分类号： H01J29/085 , H01J31/127
摘要： A flat panel display device capable of reducing charging of phosphors and disposing spacers easily and accurately. The flat panel display device has a rear substrate including an insulating substrate provided with many cold cathode elements for emitting electrons, a display substrate including a light-transmissive substrate disposed to face the rear substrate, and phosphors disposed on the light-transmissive substrate for generating light when excited by electron beams from the cold cathode elements, and a peripheral frame member. Provided on the light-transmissive substrate is a metal sheet perforated with plural fine holes arranged in a matrix configuration and having the phosphors disposed therewithin to form a light-emissive region.
摘要翻译：一种平板显示装置，其能够容易且准确地减少荧光体的充电和配置间隔物。平板显示装置具有：背面基板，具有设置有用于发射电子的许多冷阴极元件的绝缘基板;显示基板，包括设置在背面基板上的透光基板;以及荧光体，设置在透光基板上，用于产生由来自冷阴极元件的电子束激发的光，以及周边框架部件。在透光性基板上设置有以多个配置成矩阵状的细孔的多孔金属片，并配置有磷光体，形成发光区域。

36. 发明申请

US20060077626A1 Flat image display device 审中-公开
标题翻译：平面图像显示装置
公开(公告)号：US20060077626A1
公开(公告)日：2006-04-13
申请号：US11104665
申请日：2005-04-13
申请人： Nobuo Masuoka , Yoshie Kodera , Tetsu Ohishi , Masakazu Sagawa , Akinori Maeda
发明人： Nobuo Masuoka , Yoshie Kodera , Tetsu Ohishi , Masakazu Sagawa , Akinori Maeda
IPC分类号： G06F1/16
CPC分类号： H01J29/862 , H01J11/10 , H01J11/34 , H01J31/12 , H01J2329/862
摘要： The present invention provides a flat image display device having a support frame that is compatible with a large flat image display device and has a high bonding strength. The invention relates to a flat image display device including: a display substrate; a back substrate disposed opposite the display substrate with a specified clearance therebetween; and a frame glass disposed around the back substrate and the display substrate, for supporting the substrates with the specified clearance therebetween. The invention is characterized in that the frame glass includes frame glasses whose ends each have at least two steps and the stepped ends are in engagement with each other and bonded together.
摘要翻译：本发明提供一种平板图像显示装置，其具有与大平面图像显示装置兼容并具有高粘合强度的支撑框架。本发明涉及一种平面图像显示装置，包括：显示基板; 背面基板，其与显示基板相对设置，其间具有指定的间隙; 以及设置在所述背面基板和所述显示基板的周围的框架玻璃，用于以规定的间隙支撑所述基板。本发明的特征在于，框架玻璃包括其端部各自具有至少两个台阶并且台阶端部彼此接合并结合在一起的框架玻璃。

37. 发明授权

US06614169B2 Display device using thin film cathode and its process 失效
标题翻译：使用薄膜阴极的显示装置及其工艺
公开(公告)号：US06614169B2
公开(公告)日：2003-09-02
申请号：US09791699
申请日：2001-02-26
申请人： Toshiaki Kusunoki , Mutsumi Suzuki , Masakazu Sagawa
发明人： Toshiaki Kusunoki , Mutsumi Suzuki , Masakazu Sagawa
IPC分类号： H01J162
CPC分类号： B82Y10/00 , H01J1/312 , H01J2329/00
摘要： Disclosed is a display device with improved brightness achieved by increasing electron emission efficiency of a thin film cathode. Phosphors are irradiated with electrons emitted to a vacuum through a flat thin film which is thinner than 5 nm and is disposed so as to face the phosphors. A top electrode for emitting the electrons is formed by stacking thin films of Ir, Pt, and Au, and performing a heat treatment so as to reconstruct the top electrode to have a structure in which thick island parts and a flat thin film part mixedly exist.
摘要翻译：公开了通过增加薄膜阴极的电子发射效率而获得的亮度提高的显示装置。用通过比5nm薄的扁平薄膜发射到真空的电子被荧光体照射，并且被设置为面对荧光体。用于发射电子的顶部电极通过堆叠Ir，Pt和Au的薄膜而形成，并进行热处理，以便重建顶部电极以具有其中稠岛部分和平坦薄膜部分混合存在的结构。

38. 发明授权

US6127255A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US6127255A
公开(公告)日：2000-10-03
申请号：US943729
申请日：1997-10-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/4763 , H01L21/469
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由元件分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的有源区的主表面上形成MISFET。所公开的方法包括在包括最上面布线的布线上形成绝缘膜，最上面的布线在相邻最上布线之间具有间隙。绝缘膜包括在布线和相邻的最上布线之间的间隙中形成氧化硅膜，并且在氧化硅膜上形成氮化硅膜，通过等离子体化学气相沉积形成氮化硅膜。氧化硅膜形成为具有至少相邻最上面布线之间的间隙的一半的厚度，其中氮化硅膜比氧化硅膜厚。

39. 发明授权

US5739589A Semiconductor integrated circuit device process for fabricating the same and apparatus for fabricating the same 失效
标题翻译：用于制造该半导体集成电路器件的半导体集成电路器件及其制造方法
公开(公告)号：US5739589A
公开(公告)日：1998-04-14
申请号：US657194
申请日：1996-06-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/44 , H01L21/48
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

40. 发明授权

US5202275A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5202275A
公开(公告)日：1993-04-13
申请号：US496330
申请日：1990-03-20
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在所述衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

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