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31. 发明授权

US07470953B2 Insulated gate type semiconductor device and manufacturing method thereof 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：US07470953B2
公开(公告)日：2008-12-30
申请号：US10573793
申请日：2004-10-06
申请人： Hidefumi Takaya , Kimimori Hamada , Akira Kuroyanagi , Yasushi Okura , Norihito Tokura
发明人： Hidefumi Takaya , Kimimori Hamada , Akira Kuroyanagi , Yasushi Okura , Norihito Tokura
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/42368 , H01L29/7397 , H01L29/7811
摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N− drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.
摘要翻译：本发明旨在提供可以容易地制造的绝缘栅型半导体器件及其制造方法，同时实现更高的耐压设计和较低的导通电阻设计。半导体器件包括N +源极区31，N +漏极区11，P-体区41和N漂移区12.通过挖掘半导体器件的上侧的一部分，形成栅沟槽21。栅极沟槽21包含栅电极22.P浮动区51设置在栅极沟槽21的下方。可以形成与栅极沟槽21的深度不同的另外的沟槽35，设置在沟槽25下方的P浮动区域54。

32. 发明申请

US20050227438A1 Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050227438A1
公开(公告)日：2005-10-13
申请号：US11140756
申请日：2005-05-31
申请人： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
发明人： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7802 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/167 , H01L29/34 , H01L29/41741 , H01L29/456 , H01L29/66712 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977 , H01L2924/00
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译：一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。该器件具有降低的导通电阻。

33. 发明申请

US20050212176A1 Heated medium supplying method and structure for secondary molding of resin molding component 失效
标题翻译：加热介质供应方法和结构，用于树脂成型部件的二次成型
公开(公告)号：US20050212176A1
公开(公告)日：2005-09-29
申请号：US11086218
申请日：2005-03-22
申请人： Hidehisa Nasu , Akira Kuroyanagi , Masato Ichikawa , Akira Sahashi
发明人： Hidehisa Nasu , Akira Kuroyanagi , Masato Ichikawa , Akira Sahashi
IPC分类号： B29C45/26 , B29C45/00 , B29C45/14 , B29C45/17 , B29C45/72 , B29C45/73 , B29L23/00
CPC分类号： B29C45/0062 , B29C65/103 , B29C65/42 , B29C65/542 , B29C66/0242 , B29C66/1312 , B29C66/547 , B29C2045/14877
摘要： A hot-air supply structure (1) comprises a hot air generator (20) and a housing (15) formed in the neighborhood of a hot-air inlet (81) of a molded component M in a die (10). A nozzle (21) is formed at the forward end of the hot-air generator, and an ejection port (211b) is formed on the side wall portion of the forward end needle unit (211) of the nozzle. The housing includes a support hole (151) in the nozzle, a relief hole (152), a flow path communication passage (153) and a bypass (154). The ejection port is movable between a first position to discharge the cool or warm air into the atmosphere through the bypass from the relief hole and a second position to introduce hot air into the flow path (8) of the molded component through the inlet (81) and the passage (153).
摘要翻译：热空气供给结构（1）包括在模具（10）中形成在模制部件M的热空气入口（81）附近的热空气发生器（20）和壳体（15）。在热风发生器的前端形成有喷嘴（21），在喷嘴的前端针单元（211）的侧壁部形成有喷出口（211b）。壳体包括喷嘴中的支撑孔（151），释放孔（152），流路连通通道（153）和旁路（154）。喷射口可以在第一位置和第二位置之间移动，第一位置通过旁路将冷空气或暖空气从释放孔排出到第二位置，以便通过入口（81）将热空气引入模制部件的流动路径（8））和通道（153）。

34. 发明授权

US06525400B2 Semiconductor memory device and method of manufacturing the same 失效
公开(公告)号：US06525400B2
公开(公告)日：2003-02-25
申请号：US10078506
申请日：2002-02-21
申请人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
发明人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
IPC分类号： H01L2900
CPC分类号： H01L29/7883 , H01L21/28273
摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

35. 发明授权

US06365458B1 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06365458B1
公开(公告)日：2002-04-02
申请号：US09661572
申请日：2000-09-14
申请人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
发明人： Tetsuo Fujii , Minekazu Sakai , Akira Kuroyanagi
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.
摘要翻译：在半导体衬底的表面上形成栅极氧化膜。在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。在栅极绝缘膜上形成杂质浓度低的第一硅膜。在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。通过绝缘膜在第二硅膜上形成第三硅膜。第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。

36. 发明授权

US5689130A Vertical semiconductor device with ground surface providing a reduced ON resistance 失效
标题翻译：具有地面的垂直半导体器件提供降低的导通电阻
公开(公告)号：US5689130A
公开(公告)日：1997-11-18
申请号：US409900
申请日：1995-03-22
申请人： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
发明人： Yoshifumi Okabe , Masami Yamaoka , Akira Kuroyanagi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/304 , H01L21/336 , H01L29/06 , H01L29/167 , H01L29/34 , H01L29/417 , H01L29/45 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L23/48 , H01L23/52
CPC分类号： H01L29/66712 , H01L21/28 , H01L21/28512 , H01L21/304 , H01L29/0657 , H01L29/34 , H01L29/41741 , H01L29/7802 , H01L29/167 , H01L29/456 , H01L2924/0002 , H01L2924/10158 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/964 , Y10S438/977
摘要： A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
摘要翻译：一种半导体器件，包括包含砷作为杂质的N型半导体衬底，形成在N型半导体衬底的主表面上的第一电极，形成在N型半导体衬底的另一表面上的接地表面，第二电极，其形成在地表面上并与N型半导体衬底欧姆接触，形成在N型半导体衬底中的半导体元件和在其第一电极和第二电极之间的流动电流。该器件具有降低的导通电阻。

37. 发明授权

US5654560A Semiconductor device with current detecting function and method of producing the same 失效
标题翻译：具有电流检测功能的半导体器件及其制造方法
公开(公告)号：US5654560A
公开(公告)日：1997-08-05
申请号：US475096
申请日：1995-06-07
申请人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
发明人： Toshiaki Nishizawa , Akira Kuroyanagi , Tsuyoshi Yamamoto , Norihito Tokura
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02 , H01L27/04 , H01L29/74
CPC分类号： H01L29/66712 , H01L27/0248 , H01L29/7811 , H01L29/7815 , Y10S148/126
摘要： A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part. The subordinate well region is made shallower than the principal well region illustratively by use of a mask having narrower apertures through which to form the former region. This causes a reach-through to occur in the principal current part with its well region having a shorter distance to the high density substrate, and not in the detection part with its well region having a longer distance to the substrate.
摘要翻译：一种具有电流检测功能的功率半导体器件，包括检测部件，该检测部件包括比主电流部件更好的达到耐受电压能力的元件。功率半导体器件包括诸如DMOS，IGBT或BPT单元的元件。设备的一个区域作为检测部分，另一个作为主要的当前部分。检测部分和主要电流部分共同作为其公共电极具有第一导电类型的低密度层的高密度基板。低密度层的表面分别载有第二导电类型的主要和次要的阱区。主阱区域的表面具有作为主电流部分的另一个电极的第一导电类型的表面电极区域; 下位阱区域的表面带有用作检测部分的另一电极的第一导电类型的表面电极区域。通过使用具有较窄孔径的掩模来形成下一个井区域使其比主井区域浅，以形成前区域。这导致在主电流部分中出现通孔，其阱区具有与高密度衬底相距较短的距离，而不在其阱区具有与衬底相距较远的检测部分中。

38. 发明授权

US5592004A Silicon nitride film having a short absorption wavelength and surrounding crystal-like grain boundaries 失效
标题翻译：具有短的吸收波长并且包围晶体状晶界的氮化硅膜
公开(公告)号：US5592004A
公开(公告)日：1997-01-07
申请号：US534976
申请日：1995-09-28
申请人： Muneo Tamura , Takeshi Yamauchi , Katuhide Niwa , Takeshi Fukazawa , Akira Kuroyanagi , Tooru Yamaoka
发明人： Muneo Tamura , Takeshi Yamauchi , Katuhide Niwa , Takeshi Fukazawa , Akira Kuroyanagi , Tooru Yamaoka
IPC分类号： H01L21/8247 , C23C16/34 , H01L21/314 , H01L21/318 , H01L23/31 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/06 , H01L29/78
CPC分类号： C23C16/347 , H01L21/3185 , H01L23/3171 , H01L2924/0002
摘要： A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.
摘要翻译：半导体器件包括半导体元件。氮化硅膜覆盖半导体元件。氮化硅膜由SiXNYHZ制成，其中X，Y和Z分别表示Si，N和H的原子级分。氮化硅膜涉及短于254nm的光吸收边缘波长。在氮化硅膜表面的晶状晶界包围的区域的平均面积为4.5×10 4 nm 2以上。半导体元件可以包括可通过暴露于紫外线而从其中擦除信息的存储元件。

39. 发明授权

US5534454A Method of producing a semiconductor device having accurate current detection 失效
标题翻译：制造具有精确电流检测的半导体器件的方法
公开(公告)号：US5534454A
公开(公告)日：1996-07-09
申请号：US385553
申请日：1995-02-08
申请人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
发明人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
IPC分类号： H01L21/336 , H01L21/76 , H01L27/02 , H01L27/04 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L29/7815 , H01L27/0248 , H01L29/0619 , H01L29/0696 , H01L29/1095
摘要： A power DMOS semiconductor device is producible with standard processes and provides improved current detecting accuracy. The device involves main wells (41), subwells (42), and a line well (43), which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate (1) with well forming impurities. The line well surrounds the subwells with a predetermined distance away from the subwells, to relax an electric field on the surface of the substrate. Gate electrodes (71, 72) are patterned to form a line opening (10), which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.
摘要翻译：功率DMOS半导体器件可通过标准工艺生产，并提供改进的电流检测精度。该装置包括主井（41），底孔（42）和一条管井（43），其独立于主井和下井。这些阱通过掺杂具有良好形成杂质的半导体衬底（1）的表面而形成。线条井围绕底孔以预定的距离离开底孔，以松弛基底表面上的电场。栅电极（71,72）被图案化以形成围绕底孔的线路开口（10）。当通过用形成孔的杂质掺杂衬底的表面来形成线时，线路开口用作掩模。因此，线槽与相邻的底座之间的区域的宽度不会波动。

40. 发明授权

US5250449A Vertical type semiconductor device and method for producing the same 失效
标题翻译：垂直型半导体装置及其制造方法
公开(公告)号：US5250449A
公开(公告)日：1993-10-05
申请号：US767313
申请日：1991-09-30
申请人： Akira Kuroyanagi , Masami Yamaoka , Yoshifumi Okabe
发明人： Akira Kuroyanagi , Masami Yamaoka , Yoshifumi Okabe
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66719 , H01L29/1095 , H01L29/66712 , H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/402 , H01L29/42368 , Y10S148/126
摘要： The present invention has as an object the provision of a vertical type semiconductor device whereby miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.The line width of the gate electrode is made smaller to meet the demand for miniaturization of the cell, but the distance between the channel regions diffused into the portions below the gate at the time of double diffusion is kept to be virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. Here, the reason for making the line width of the gate electrode smaller is for securing an area for the source contact.The point is that, while the width of the gate electrode is set to be smaller, the mask members as the mask for double diffusion, having the width allowing the source region to diffuse to the portion under the gate, are attached to the side walls of the gate electrode.Thereby, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.
摘要翻译：本发明的目的是提供一种垂直型半导体器件，由此可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。使栅电极的线宽变小以满足电池小型化的需要，但是扩散到双扩散时的栅极下方的沟道区域之间的距离保持实质上等于具有低JFET电阻分量的较大单元尺寸的器件。这里，使栅电极的线宽变小的原因是为了确保源极接触的面积。要注意的是，尽管栅电极的宽度被设定得较小，但是具有允许源极区域扩散到栅极下方的宽度的双扩散掩模的掩模构件附接到侧壁的栅电极。由此，可以实现电池的小型化和降低的导通电阻，而不会损害器件的功能。

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