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31. 发明授权

US5216266A Semiconductor memory device having memory cells formed in trench and manufacturing method therefor 失效
标题翻译：具有形成沟槽的存储单元的半导体存储器件及其制造方法
公开(公告)号：US5216266A
公开(公告)日：1993-06-01
申请号：US682521
申请日：1991-04-09
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7827 , H01L27/10841
摘要： A semiconductor memory device includes a memory cell formed in a trench. The trench is formed by a bottom wall formed of a semiconductor substrate and a sidewall extending from the bottom wall and formed of the semiconductor substrate and an insulation layer thereon. A capacitor includes a first electrode formed in the semiconductor substrate, a dielectric film being in contact with the first electrode and formed on the bottom wall and the sidewall portion formed of the semiconductor substrate, and a second electrode formed on the dielectric film. A field effect transistor includes, a gate electrode, and second conductivity type first and second impurity regions formed in a semiconductor sidewall layer. The semiconductor sidewall layer is formed on the sidewall portion formed of the insulation layer. The gate electrode is formed on a side surface of the semiconductor sidewall layer in the trench with an insulating film interposed therebetween. An interconnection layer is formed above the gate electrode in the trench. By forming all the elements constituting the memory cell in the trench, the memory cell can be effectively miniaturized and no parasitic MOS transistor is formed. Isolation width between the memory cells can be reduced. Capacitance of the capacitor can be increased without forming a field effect transistor having an extremely short channel length.
摘要翻译：半导体存储器件包括形成在沟槽中的存储单元。沟槽由半导体衬底形成的底壁和从底壁延伸并由半导体衬底和绝缘层形成的侧壁形成。电容器包括形成在半导体衬底中的第一电极，与第一电极接触并形成在底壁上的电介质膜和由半导体衬底形成的侧壁部分，以及形成在电介质膜上的第二电极。场效应晶体管包括形成在半导体侧壁层中的栅电极和第二导电类型的第一和第二杂质区。半导体侧壁层形成在由绝缘层形成的侧壁部上。栅电极形成在沟槽中的半导体侧壁层的侧表面上，隔着绝缘膜。在沟槽中的栅电极上形成互连层。通过在沟槽中形成构成存储单元的所有元件，可以有效地使存储单元小型化，并且不形成寄生MOS晶体管。可以减少存储单元之间的隔离宽度。可以增加电容器的电容而不形成具有极短通道长度的场效应晶体管。

32. 发明授权

US4996168A Method for manufacturing P type semiconductor device employing diffusion of boron glass 失效
标题翻译：制造采用硼玻璃扩散的P型半导体器件的方法
公开(公告)号：US4996168A
公开(公告)日：1991-02-26
申请号：US265448
申请日：1988-11-01
申请人： Hiroji Ozaki , Shigeo Nagao
发明人： Hiroji Ozaki , Shigeo Nagao
IPC分类号： H01L21/033 , H01L21/225 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/033 , H01L21/2255 , H01L21/823814 , H01L27/108
摘要： An improved method for manufacturing P type semiconductor device such as used for memories is disclosed. Channeling such as caused by an ion implantation process is prevented by adopting a diffusion method to diffuse boron (7) from a boron glass formed on a layer of polysilicon or silicon oxide on a semiconductor substrate. This method provides a semiconductor device with shallow P type impurity diffusion regions.
摘要翻译：公开了一种用于制造用于存储器的P型半导体器件的改进方法。通过采用扩散法，在半导体衬底上从形成在多晶硅或氧化硅层上的硼玻璃扩散硼（7）来防止诸如由离子注入工艺引起的沟道。该方法提供了具有浅P型杂质扩散区域的半导体器件。

33. 发明授权

US4702796A Method for fabricting a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4702796A
公开(公告)日：1987-10-27
申请号：US931583
申请日：1986-11-14
申请人： Masayuki Nakajima , Shinichi Sato , Akira Tokui , Akira Kawai , Masao Nagatomo , Hiroji Ozaki
发明人： Masayuki Nakajima , Shinichi Sato , Akira Tokui , Akira Kawai , Masao Nagatomo , Hiroji Ozaki
IPC分类号： H01L21/74 , H01L21/8242 , H01L23/556 , H01L21/04 , B44C1/22 , H01L21/22 , H01L21/306
CPC分类号： H01L27/10844 , H01L21/74 , H01L23/556 , H01L2224/16245 , H01L2224/48247 , Y10S438/965
摘要： The present invention is a method for fabricating a semiconductor device, wherein impurity is selectively diffused to surround a region (7) of a second conductivity type as a bit line formed on a semiconductor substrate (1), thereby forming an impurity diffused region (9) of a first conductivity type having high density and, by extending the impurity diffused region (9) in the element separating step to form a high density region of the first conductivity type having high density.
摘要翻译：本发明是一种制造半导体器件的方法，其中杂质被选择性扩散以包围形成在半导体衬底（1）上的位线的第二导电类型的区域（7），从而形成杂质扩散区域（9 ），并且通过在元件分离步骤中扩展杂质扩散区域（9）以形成具有高密度的第一导电类型的高密度区域。

34. 发明授权

US06319733B1 Method of manufacturing semiconductor device, semiconductor equipment and manufacturing system 失效
标题翻译：制造半导体器件，半导体器件和制造系统的方法
公开(公告)号：US06319733B1
公开(公告)日：2001-11-20
申请号：US09395219
申请日：1999-09-14
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： G01R3126
CPC分类号： H01L22/26
摘要： A manufacturing system compares information of foreign matter sensed by semiconductor equipment from on a semiconductor substrate with a selection reference thereby selecting optimum semiconductor equipment corresponding to the information of the foreign matter from a plurality of semiconductor equipment and processing the semiconductor substrate. Thus, a method of manufacturing a semiconductor device capable of improving the yield of the semiconductor device as well as a manufacturing system and semiconductor equipment to which the manufacturing method is applied, and a semiconductor device manufactured by the same are obtained.
摘要翻译：制造系统将来自半导体衬底的半导体设备感应的异物的信息与选择基准进行比较，从而从多个半导体设备中选择与异物的信息相对应的最佳半导体设备并处理半导体衬底。因此，获得能够提高半导体器件的产量的半导体器件的制造方法以及应用制造方法的制造系统和半导体器件以及由其制造的半导体器件。

35. 发明授权

US6128403A Wafer map analysis aid system, wafer map analyzing method and wafer processing method 失效
标题翻译：晶圆图分析辅助系统，晶圆图分析方法和晶圆加工方法
公开(公告)号：US6128403A
公开(公告)日：2000-10-03
申请号：US026184
申请日：1998-02-19
申请人： Hiroji Ozaki
发明人： Hiroji Ozaki
IPC分类号： G06K9/00 , G06T7/00 , H01L21/02 , H01L21/66
CPC分类号： G06T7/0004 , H01L22/20 , G06T2200/24 , G06T2207/30148
摘要： In order to solve various problems of a wafer, two-dimensional analysis using a wafer map is aided. An image of the wafer map is classified and displayed on a screen for each item such as a manufacturing step, a device and inspection. A trend chart is also attached in addition to the image of the wafer map.
摘要翻译：为了解决晶片的各种问题，有助于使用晶片图的二维分析。将晶片图的图像分类并显示在诸如制造步骤，装置和检查之类的每个项目的屏幕上。除了晶片图的图像之外，还附加了趋势图。

36. 发明授权

US4763182A Semiconductor memory device with deep bit-line channel stopper 失效
标题翻译：具有深位线通道阻塞的半导体存储器件
公开(公告)号：US4763182A
公开(公告)日：1988-08-09
申请号：US941216
申请日：1986-12-12
申请人： Hiroji Ozaki , Shinichi Sato , Akira Tokui , Akira Kawai , Masayuki Nakajima , Masao Nagatomo
发明人： Hiroji Ozaki , Shinichi Sato , Akira Tokui , Akira Kawai , Masayuki Nakajima , Masao Nagatomo
IPC分类号： H01L27/10 , G11C11/34 , H01L21/74 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L27/10844 , H01L21/74 , H01L27/10805 , H01L29/0847 , H01L29/1083
摘要： A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.
摘要翻译：半导体存储器件包括形成有电荷存储区域（5）的第一导电型半导体衬底（1）和用作位线的第二导电类型区域（6），以及第一导电型高浓度区域（8,11 形成浓度高于半导体衬底（1）的至少一位数，以分别包围电荷存储区域（5）和位线区域（6）。因此，可以在高度集中区域（8）和电荷存储区域（5）之间以及高度集中区域（11）和位线区域（6）之间的界面中限定抵抗电子的势垒，从而防止故障通过放射线如α射线的发生。

37. 发明申请

US20110014783A1 SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20110014783A1
公开(公告)日：2011-01-20
申请号：US12888995
申请日：2010-09-23
申请人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/283
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

38. 发明申请

US20100159687A1 SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20100159687A1
公开(公告)日：2010-06-24
申请号：US12719524
申请日：2010-03-08
申请人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu OKAZAKI , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

39. 发明申请

US20070155153A1 Semiconductor device having electrode and manufacturing method thereof 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US20070155153A1
公开(公告)日：2007-07-05
申请号：US11649208
申请日：2007-01-04
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada
IPC分类号： H01L21/44
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
摘要翻译：半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。

40. 发明申请

US20070164342A1 Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070164342A1
公开(公告)日：2007-07-19
申请号：US11651965
申请日：2007-01-11
申请人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
发明人： Tsutomu Okazaki , Motoi Ashida , Hiroji Ozaki , Tsuyoshi Koga , Daisuke Okada , Masamichi Matsuoka
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.
摘要翻译：形成存储器栅互连等的多晶硅膜包括从位于控制栅互连的一个侧表面上的部分延伸到与控制栅互连的一侧相对的一侧的部分，并且该部分用作焊盘一部分。形成接触孔以露出焊盘部分。位于控制栅极互连的一个侧面上的多晶硅膜的一部分的高度设定为等于或低于控制栅极互连的高度，使得形成存储器栅互连等的多晶硅膜不会二维重叠控制门互连。因此，可以获得具有增加的工艺裕量的半导体存储器件。

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