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31. 发明授权

US07499582B2 Method for inspecting a defect in a photomask, method for manufacturing a semiconductor device and method for producing a photomask 失效
标题翻译：用于检查光掩模中的缺陷的方法，用于制造半导体器件的方法和用于制造光掩模的方法
公开(公告)号：US07499582B2
公开(公告)日：2009-03-03
申请号：US10878384
申请日：2004-06-29
申请人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
发明人： Toshiya Kotani , Suigen Kyoh , Shinji Yamaguchi , Soichi Inoue
IPC分类号： G06K9/00
CPC分类号： G03F1/84 , G06T7/001 , G06T2207/30148
摘要： There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
摘要翻译：公开了一种用于检查光掩模中的缺陷的方法，其通过使用匹配掩模数据的图形数据或通过对掩模数据进行校正至少与线宽相关的处理转换差来产生。该方法包括以下步骤。通过校正掩模数据的图案以便通过使用图形数据基本上匹配要产生的光掩模的图案的平面形状来产生检查数据。将生成的光掩模的图案与检查数据的图案进行比较。提取检查数据的图案的平面形状和所生成的光掩模的图案不匹配的部分。缺陷与刨床形状不匹配的部分不同。

32. 发明申请

US20090021711A1 METHOD OF INSPECTING EXPOSURE SYSTEM AND EXPOSURE SYSTEM 审中-公开
标题翻译：检查曝光系统和曝光系统的方法
公开(公告)号：US20090021711A1
公开(公告)日：2009-01-22
申请号：US12173943
申请日：2008-07-16
申请人： Takashi Sato , Soichi Inoue
发明人： Takashi Sato , Soichi Inoue
IPC分类号： G03B27/42 , G01B11/14
CPC分类号： G03F7/706 , G03B27/42 , G03F1/44
摘要： A method of inspecting an exposure system uses a mask pattern including a first and a second mask pattern, the first pattern being formed in a line-and-space of a first pitch, the second pattern being disposed in parallel with the first mask pattern and formed in a line-and-space of a second pitch. The method includes illuminating the mask pattern with inspection light at a first angle with the optical axis of the illumination light from a light source, allowing the first mask pattern to diffract the inspection light to generate first diffraction light, and allowing the second mask pattern to diffract the inspection light to generate second diffraction light. The first angle is to allow the first diffraction light to be diffracted asymmetrically with the optical axis into the projection optical system and the second diffraction light to be diffracted symmetrically with the optical axis into the projection optical system.
摘要翻译：检查曝光系统的方法使用包括第一和第二掩模图案的掩模图案，第一图案形成在第一间距的直线和间隔中，第二图案与第一掩模图案平行设置，形成在第二间距的线和空间中。该方法包括用来自光源的照明光的光轴以第一角度的检查光照亮掩模图案，允许第一掩模图案衍射检查光以产生第一衍射光，并允许第二掩模图案衍射检查光以产生第二衍射光。第一角度是允许第一衍射光被光轴不对称地衍射到投影光学系统中，并且第二衍射光将被光轴对称地衍射到投影光学系统中。

33. 发明申请

US20080232671A1 MASK PATTERN VERIFYING METHOD 有权
标题翻译：掩模图验证方法
公开(公告)号：US20080232671A1
公开(公告)日：2008-09-25
申请号：US12052066
申请日：2008-03-20
申请人： Mitsuyo ASANO , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
发明人： Mitsuyo ASANO , Shinji Yamaguchi , Satoshi Tanaka , Soichi Inoue , Masamitsu Itoh , Osamu Ikenaga
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G03F1/86 , G06T2207/10056 , G06T2207/30148
摘要： A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.
摘要翻译：掩模图案验证方法包括从掩模图案的设计数据获得关于热点的第一信息，获得关于实际形成在光掩模上的掩模图案的第二信息，以及确定实际形成在光掩模上的掩模图案的测量点基于第一和第二信息。

34. 发明授权

US07371483B2 Method for manufacturing mask for focus monitoring, and method for manufacturing semiconductor device 失效
标题翻译：用于制造焦点监视用掩模的方法以及半导体装置的制造方法
公开(公告)号：US07371483B2
公开(公告)日：2008-05-13
申请号：US10830399
申请日：2004-04-23
申请人： Shingo Kanamitsu , Takashi Hirano , Kyoko Izuha , Soichi Inoue , Shinichi Ito
发明人： Shingo Kanamitsu , Takashi Hirano , Kyoko Izuha , Soichi Inoue , Shinichi Ito
IPC分类号： G03F9/00
CPC分类号： G03F1/32 , G03F1/44 , Y10S430/143
摘要： Disclosed is a method for manufacturing a mask for focus monitoring, comprising forming a first opening portion and a second opening portion in a surface region of a transparent substrate, the second opening portion having a pattern shape corresponding to a pattern shape of the first opening portion, and being surrounded by a stack film formed of a halftone film on the transparent substrate and an opaque film on the halftone film, and radiating a charged beam onto a first region which includes an edge of the second opening portion and inside and outside regions which are respectively located inward and outward of the edge of the second opening portion, to etch that part of the transparent substrate which corresponds to the inside region.
摘要翻译：本发明公开了一种制造用于聚焦监测的掩模的方法，包括在透明基板的表面区域中形成第一开口部分和第二开口部分，所述第二开口部分具有与第一开口部分的图案形状对应的图案形状并且被由透明基板上的半色调膜形成的叠层膜和半色调膜上的不透明膜包围，并且将带电束辐射到包括第二开口部分的边缘和内部和外部区域的第一区域上，分别位于第二开口部分的边缘的内侧和外侧，以蚀刻对应于内部区域的透明基板的那部分。

35. 发明申请

US20080072208A1 Mask defect inspecting method, semiconductor device manufacturing method, mask defect inspecting apparatus, defect influence map generating method, and computer program product 有权
标题翻译：掩模缺陷检查方法，半导体器件制造方法，掩模缺陷检查装置，缺陷影响图生成方法和计算机程序产品
公开(公告)号：US20080072208A1
公开(公告)日：2008-03-20
申请号：US11980640
申请日：2007-10-31
申请人： Shinji Yamaguchi , Soichi Inoue , Satoshi Tanaka , Mari Inoue
发明人： Shinji Yamaguchi , Soichi Inoue , Satoshi Tanaka , Mari Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/84
摘要： A mask defect inspecting method comprises preparing detection sensitivities of defects on a plurality of portions of a mask pattern on a photomask, the detection sensitivities being determined according to influences of the defects upon a wafer, and inspecting defects on the plurality of portions based on the detection sensitivities.
摘要翻译：掩模缺陷检查方法包括：对光掩模上的掩模图案的多个部分上的缺陷的检测灵敏度进行准备，检测灵敏度根据晶片上的缺陷的影响确定，并且基于所述多个部分检查多个部分的缺陷检测灵敏度。

36. 发明申请

US20070177127A1 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
标题翻译：晶片平坦度评估方法，执行评估方法的晶片平整度评估装置，使用评估方法的晶片制造方法，使用评估方法的晶片质量保证方法，使用评估方法的半导体器件制造方法和使用由评估方法
公开(公告)号：US20070177127A1
公开(公告)日：2007-08-02
申请号：US11710552
申请日：2007-02-26
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
摘要翻译：公开了一种晶片平坦度评估方法，其包括测量晶片的前后表面形状。测量的晶圆正面分为几个部位。然后，根据要评估的位置的位置选择平坦度计算方法，并获得晶片表面的平坦度。

37. 发明授权

US07230680B2 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
公开(公告)号：US07230680B2
公开(公告)日：2007-06-12
申请号：US10739275
申请日：2003-12-19
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58 , G03B27/42
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

38. 发明授权

US07208423B2 Semiconductor device fabrication method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07208423B2
公开(公告)日：2007-04-24
申请号：US10107298
申请日：2002-03-28
申请人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
发明人： Koji Hashimoto , Soichi Inoue , Kazuhiro Takahata , Kei Yoshikawa
IPC分类号： H01L21/302 , G03C5/00 , B44C1/22
CPC分类号： G03F7/0035 , H01L21/0338 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L21/823475 , H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
摘要翻译：在工作薄膜（3）上的硬掩模材料膜（4）上的曝光分辨率的限制的尺寸形成抗蚀剂图案（5）。使用抗蚀剂图案（5）作为掩模来处理材料膜（4）。由此形成硬掩模图案（6）。由此，在非选择区域（6b）上形成具有开口（7a）的抗蚀剂图案（7），掩模图案中的选择区域（6a）通过该开口暴露。仅通过开口（7a）暴露的掩模图案（6a）通过进行选择蚀刻而变薄，通过使用掩模图案（6）蚀刻工作膜（3）。由此形成工作胶片图案（8），其包括具有限制曝光分辨率的尺寸宽度的宽图案部分（8a）和尺寸不大于该尺寸的尺寸的纤薄图案部分（8a）曝光分辨率的限制。

39. 发明申请

US20070071306A1 Inspection method and photomask 失效
标题翻译：检验方法和光掩模
公开(公告)号：US20070071306A1
公开(公告)日：2007-03-29
申请号：US11606121
申请日：2006-11-30
申请人： Kazuya Fukuhara , Satoshi Tanaka , Soichi Inoue
发明人： Kazuya Fukuhara , Satoshi Tanaka , Soichi Inoue
IPC分类号： G03F1/00 , G03C5/00 , G06K9/00
CPC分类号： G03F7/70566 , G03F7/706
摘要： An inspection method, includes obtaining a first optical characteristic of a projection optical system by transferring an image of an aberration measurement unit of a photomask on a first resist film coated on a first wafer by use of a first polarized exposure light; obtaining a second optical characteristic of the projection optical system by transferring the image of the aberration measurement unit on a second resist film coated on a second wafer by use of a second exposure light having a polarization state different from the first exposure light; and calculating a difference between the first and second optical characteristics.
摘要翻译：一种检查方法，包括通过使用第一偏振曝光光在涂覆在第一晶片上的第一抗蚀膜上转印光掩模的像差测量单元的图像来获得投影光学系统的第一光学特性; 通过使用具有与第一曝光光不同的偏振状态的第二曝光光，将像差测量单元的图像转印在涂覆在第二晶片上的第二抗蚀剂膜上，从而获得投影光学系统的第二光学特性; 以及计算第一和第二光学特性之间的差。

40. 发明授权

US07148138B2 Method of forming contact hole and method of manufacturing semiconductor device 失效
标题翻译：形成接触孔的方法和制造半导体器件的方法
公开(公告)号：US07148138B2
公开(公告)日：2006-12-12
申请号：US10969996
申请日：2004-10-22
申请人： Shoji Mimotogi , Hiroko Nakamura , Kazuya Fukuhara , Satoshi Tanaka , Soichi Inoue
发明人： Shoji Mimotogi , Hiroko Nakamura , Kazuya Fukuhara , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L21/4763
CPC分类号： G03F7/70425 , G03F7/70466 , H01L21/76816
摘要： A method of forming a contact hole on a substrate by using a projection aligner comprising a lighting system including a light source, an aperture, and a condenser lens, a photo mask on which light from the lighting system is incident, and a projection lens for projecting the light from the photo mask onto the substrate, comprises forming a first photosensitive resist film on the substrate; exposing the first photosensitive resist film by using a photo mask in which mask patterns are cyclically arranged in a first direction and a second direction which is orthogonal to the first direction and a first aperture having light transmission parts arranged symmetrically with respect to a center point in the first direction; developing the exposed first photosensitive resist film to form first lines and linear spaces; forming a second photosensitive resist film on the substrate; exposing the second photosensitive resist film by using the photo mask and a second aperture having light transmission parts arranged symmetrically with respect to a center point in the second direction; and developing the second photosensitive resist film to form second lines and linear spaces which are orthogonal to the first lines and linear spaces.
摘要翻译：一种通过使用包括光源，孔径和聚光透镜的照明系统的投影对准器在基板上形成接触孔的方法，来自照明系统的光入射的光掩模和用于将来自光掩模的光投射到基板上，包括在基板上形成第一光敏抗蚀剂膜; 通过使用掩模图案沿与第一方向正交的第一方向和第二方向循环布置的光掩模曝光第一光敏抗蚀剂膜，以及具有相对于中心点对称布置的光传输部分的第一孔第一个方向显影第一光敏抗蚀剂膜以形成第一线和线性空间; 在所述基板上形成第二光敏抗蚀剂膜; 通过使用光掩模曝光第二光敏抗蚀剂膜，并且具有相对于第二方向的中心点对称布置的透光部分的第二孔; 并显影第二光敏抗蚀剂膜以形成与第一线和线性空间正交的第二线和线性空间。

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