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31. 发明申请

US20190057300A1 WEIGHT PREFETCH FOR IN-MEMORY NEURAL NETWORK EXECUTION 审中-公开
公开(公告)号：US20190057300A1
公开(公告)日：2019-02-21
申请号：US16160466
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
IPC分类号： G06N3/04 , G06F3/06 , G06F12/0875
摘要： The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

32. 发明申请

US20190057036A1 PROGRAMMABLE INTERFACE TO IN-MEMORY CACHE PROCESSOR 审中-公开
公开(公告)号：US20190057036A1
公开(公告)日：2019-02-21
申请号：US16160270
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
IPC分类号： G06F12/0875 , G06N3/063 , G06N3/04 , G06F3/06
摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

33. 发明申请

US20150086007A1 COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
标题翻译：紧凑型低功耗高级加密标准电路
公开(公告)号：US20150086007A1
公开(公告)日：2015-03-26
申请号：US14035508
申请日：2013-09-24
申请人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
发明人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
IPC分类号： H04L9/30
CPC分类号： H04L9/0631 , H04L2209/24
摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
摘要翻译：公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。在一个实施例中，装置包括具有替换盒和累加器的加密单元。替代方案是对每个时钟周期的一个字节执行替换操作。累加器将累积四个字节，并在四个时钟周期内执行混合列操作。加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

34. 发明申请

US20140013082A1 RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD 审中-公开
标题翻译：用于在数据字中记录数据的可重新配置的设备
公开(公告)号：US20140013082A1
公开(公告)日：2014-01-09
申请号：US13976923
申请日：2011-12-30
申请人： Amit Agarwal , Steven Hsu , Ram Krishnamurthy
发明人： Amit Agarwal , Steven Hsu , Ram Krishnamurthy
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036
摘要： Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements.
摘要翻译：公开了一种用于数据操作的系统和设备及相关方法，特别是用于SIMD操作，例如置换，移位和旋转。一种装置包括：重新定位子字边界上的数据的置换部分和重新定位小于子字宽度的数据距离的移位部分。子字宽度是可配置和可选择的，并且置换部分和移位部分可以在不同的边界宽度上操作。在第一阶段中，置换部分将数据重新定位在最近的子字边界处，并且在第二阶段中，移位部分将数据重新定位到其最终期望的位置。移位部分包括以对数级联关系设置的多级。另外，每个多级中的每个移位器是高度连接的，允许快速和精确的数据移动。

35. 发明授权

US08284766B2 Multi-core processor and method of communicating across a die 有权
标题翻译：多核处理器和跨模块通信的方法
公开(公告)号：US08284766B2
公开(公告)日：2012-10-09
申请号：US11966327
申请日：2007-12-28
申请人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
发明人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
IPC分类号： H04L12/66
CPC分类号： G06F15/17375 , G06F15/7825 , Y02D10/12 , Y02D10/13
摘要： A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network.
摘要翻译：提供了一种多核管芯，其允许使用分组交换网络和电路交换网络的资源在管芯上传送分组。

36. 发明授权

US07900160B2 System and method for illustrating a menu of insights associated with visualizations 失效
标题翻译：用于说明与可视化相关联的见解菜单的系统和方法
公开(公告)号：US07900160B2
公开(公告)日：2011-03-01
申请号：US10745500
申请日：2003-12-29
申请人： Paul B. Moody , Cynthia L. Ice , Douglas W. Conmy , Mary Elizabeth Raven , Jodi L. Coppinger , Francis D. Bermingham , Ram Krishnamurthy
发明人： Paul B. Moody , Cynthia L. Ice , Douglas W. Conmy , Mary Elizabeth Raven , Jodi L. Coppinger , Francis D. Bermingham , Ram Krishnamurthy
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： A system and method are provided for generating one or more menus having options that display insights from visualizations. The options presented in the menus enable users to determine relationships between elements of the visualization. The relationships may be displayed textually to enable user to navigate the menus using a keyboard, a text-to-voice converter, and/or pointers.
摘要翻译：提供了一种系统和方法，用于生成具有从可视化显示洞察力的选项的一个或多个菜单。菜单中显示的选项使用户能够确定可视化元素的关系。可以以文字方式显示关系，以使用户能够使用键盘，文本到语音转换器和/或指针来导航菜单。

37. 发明授权

US07860240B2 Native composite-field AES encryption/decryption accelerator circuit 有权
标题翻译：本地复合场AES加密/解密加速器电路
公开(公告)号：US07860240B2
公开(公告)日：2010-12-28
申请号：US11771723
申请日：2007-06-29
申请人： Sanu Mathew , Farhana Sheikh , Ram Krishnamurthy
发明人： Sanu Mathew , Farhana Sheikh , Ram Krishnamurthy
IPC分类号： H04K1/10
CPC分类号： H04L9/0631 , H04L2209/12
摘要： A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).
摘要翻译：一种系统包括接收伽罗瓦域GF（2k）的输入数据，将输入数据映射到复合伽罗瓦域GF（2nm），其中k = nm，将映射的输入数据输入到高级加密标准循环函数，在复合伽罗瓦域GF（2nm）中执行高级加密标准循环函数的两次或更多次迭代的执行，对高级加密标准循环函数的两次或更多次迭代的最后一次的输出数据的接收以及输出数据的映射到Galois字段GF（2k）。

38. 发明申请

US20100070894A1 FEDERATED CALENDAR ENTRY PRESENCE INDICATOR 审中-公开
标题翻译：联合日历录入指示
公开(公告)号：US20100070894A1
公开(公告)日：2010-03-18
申请号：US12211401
申请日：2008-09-16
申请人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
发明人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： A method for indicating the presence of federated calendar entries in a currently viewed time period of a calendar and/or scheduling application, includes: receiving a user's selection for a date range in a calendar and/or scheduling application; determining whether there are one or more federated calendars associated with the user's calendar and/or scheduling application; wherein in the event there are one or more federated calendars associated with the user's calendar and/or scheduling application: determining whether there are one or more events from the one or more federated calendars in the selected date range; and wherein in the event there are federated calendar events in the selected date range: generating a calendar and/or scheduling page with one or more indicators for federated calendars with events in the selected date range.
摘要翻译：一种用于指示在日历和/或调度应用的当前观看时间段中存在联合日历条目的方法，包括：在日历和/或调度应用中接收用户对日期范围的选择; 确定是否存在与用户的日历和/或调度应用相关联的一个或多个联合日历; 其中在所述事件中存在与所述用户日历和/或调度应用程序相关联的一个或多个联合日历：确定在所选择的日期范围内是否存在来自所述一个或多个联合日历的一个或多个事件; 并且其中在所述选择的日期范围内存在联合日历事件的情况下：在具有所选日期范围内的事件的联合日历中生成具有一个或多个指示符的日历和/或调度页面。

39. 发明授权

US07603398B2 Data converter and a delay threshold comparator 失效
标题翻译：数据转换器和延迟阈值比较器
公开(公告)号：US07603398B2
公开(公告)日：2009-10-13
申请号：US11094811
申请日：2005-03-31
申请人： Atul Maheshwari , Sanu K. Matthew , Mark A. Anders , Ram Krishnamurthy
发明人： Atul Maheshwari , Sanu K. Matthew , Mark A. Anders , Ram Krishnamurthy
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F9/3869 , G06F7/74
摘要： For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the data having the predetermined logical value exceeds a respective one of a plurality of reference values. The N-bit value is generated based on the outputs of the comparators. For another disclosed embodiment, a first delay element delays a signal based on a number of bits in a data value having a predetermined logical value, and a second delay element delays the signal based on a number of bits in a reference value having the predetermined logical value. A comparator then generates a bit value based on the delayed signals.
摘要翻译：对于一个公开的实施例，转换器将2N位数据转换成指示具有预定逻辑值的数据中的位数的N位值。转换器包括N个比较器，每个比较器确定具有预定逻辑值的数据中的位数是否超过多个参考值中的相应一个。基于比较器的输出产生N位值。对于另一个公开的实施例，第一延迟元件基于具有预定逻辑值的数据值中的位数来延迟信号，并且第二延迟元件基于具有预定逻辑的参考值中的位数来延迟该信号值。比较器然后基于延迟信号产生位值。

40. 发明申请

US20080104164A1 Reconfigurable SIMD vector processing system 有权
标题翻译：可重构SIMD矢量处理系统
公开(公告)号：US20080104164A1
公开(公告)日：2008-05-01
申请号：US11586810
申请日：2006-10-26
申请人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Sanu Mathew , Ram Krishnamurthy
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F2207/3828
摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
摘要翻译：系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

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