专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20110119426A1 LIST BASED PREFETCH 有权
标题翻译：以列表为前提
公开(公告)号：US20110119426A1
公开(公告)日：2011-05-19
申请号：US12696825
申请日：2010-01-29
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

32. 发明授权

US08347039B2 Programmable stream prefetch with resource optimization 失效
标题翻译：可编程流预取与资源优化
公开(公告)号：US08347039B2
公开(公告)日：2013-01-01
申请号：US12684693
申请日：2010-01-08
申请人： Peter Boyle , Norman Christ , Alan Gara , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine checks whether there exists valid data corresponding to the first memory address in an array if the first memory address is present and valid in the table. The engine increments a prefetching depth of a first stream that the first memory address belongs to and fetching a cache line associated with the first memory address from the at least one cache memory device if there is not yet valid data corresponding to the first memory address in the array. The engine determines whether prefetching of additional data is needed for the first stream within its prefetching depth. The engine prefetches the additional data if the prefetching is needed.
摘要翻译：流预取引擎在并行计算系统中执行数据检索。引擎从至少一个处理器接收加载请求。引擎评估在加载请求中请求的第一个内存地址是否存在，并且在表中有效。如果第一个存储器地址在表中存在且有效，引擎将检查是否存在与数组中的第一个存储器地址对应的有效数据。如果还没有对应于第一存储器地址的有效数据，则引擎增加第一存储器地址所属的第一流的预取深度并从至少一个高速缓冲存储器设备获取与第一存储器地址相关联的高速缓存行阵列。该引擎确定在其预取深度内的第一个流是否需要预取附加数据。如果需要预取，引擎将预取附加数据。

33. 发明授权

US08255633B2 List based prefetch 有权
标题翻译：基于列表的预取
公开(公告)号：US08255633B2
公开(公告)日：2012-08-28
申请号：US12696825
申请日：2010-01-29
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

34. 发明申请

US20060224837A1 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture 有权
公开(公告)号：US20060224837A1
公开(公告)日：2006-10-05
申请号：US11093131
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/084 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

35. 发明申请

US20060224838A1 Novel snoop filter for filtering snoop requests 有权
标题翻译：用于过滤窥探请求的新型窥探过滤器
公开(公告)号：US20060224838A1
公开(公告)日：2006-10-05
申请号：US11093152
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与其可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求写入源并将这些请求的子集转发到其相关联的处理单元。

36. 发明申请

US20060224835A1 Snoop filtering system in a multiprocessor system 有权
标题翻译：多处理器系统中的Snoop过滤系统
公开(公告)号：US20060224835A1
公开(公告)日：2006-10-05
申请号：US11093127
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing unit, with each snoop filter unit comprising a plurality of devices for receiving asynchronous snoop requests from respective memory writing sources in the computing environment; and a point-to-point interconnect comprising communication links for directly connecting memory writing sources to corresponding receiving devices; and, a plurality of parallel operating filter devices coupled in one-to-one correspondence with each receiving device for processing snoop requests received thereat and one of forwarding requests or preventing forwarding of requests to its associated processing unit. Each of the plurality of parallel operating filter devices comprises parallel operating sub-filter elements, each simultaneously receiving an identical snoop request and implementing one or more different snoop filter algorithms for determining those snoop requests for data that are determined not cached locally at the associated processing unit and preventing forwarding of those requests to the processor unit. In this manner, a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持高速缓存一致性的系统和方法，每个单元具有与其可操作耦合的相关联的高速缓存存储器系统该系统包括多个互连的窥探过滤器单元，每个窥探过滤器单元对应于相应处理单元并与其通信，每个窥探过滤器单元包括用于在计算环境中从相应存储器写入源接收异步窥探请求的多个设备 ; 以及包括用于将存储器写入源直接连接到对应的接收设备的通信链路的点对点互连; 以及与每个接收设备一一对应地耦合的多个并行操作过滤器设备，用于处理在其上接收的窥探请求，并且转发请求之一或者阻止将请求转发到其相关联的处理单元。多个并行操作过滤器装置中的每一个包括并行操作子滤波器元件，每个并行操作子滤波器元件同时接收相同的窥探请求，并且实现一个或多个不同的窥探滤波器算法，用于确定对于在相关处理中本地未被缓存的数据被确定的窥探请求并且防止将这些请求转发到处理器单元。以这种方式，减少了转发到处理单元的多个窥探请求，从而增加了计算环境的性能。

37. 发明授权

US08595389B2 Distributed performance counters 失效
标题翻译：分布式性能计数器
公开(公告)号：US08595389B2
公开(公告)日：2013-11-26
申请号：US12684738
申请日：2010-01-08
申请人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
发明人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
IPC分类号： G06F13/00 , G06F3/00 , G06F11/00
CPC分类号： G06F13/4247 , G06F9/30145 , G06F11/3476 , G06F11/348 , G06F11/3495 , G06F12/0897 , G06F2201/88 , G06F2221/2117
摘要： A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
摘要翻译：多个第一性能计数器模块耦合到多个处理核心。多个第一性能计数器模块可操作以分别收集与多个处理核心相关联的性能数据。多个第二性能计数器模块耦合到多个L2高速缓存单元，并且所述多个第二性能计数器模块可操作以分别收集与所述多个L2高速缓存单元相关联的性能数据。中央性能计数器模块可以用于协调来自多个第一性能计数器模块和多个第二性能模块的计数器数据，中央性能计数器模块，多个第一性能计数器模块和多个第二性能计数器模块通过菊花链连接连接。

38. 发明授权

US08397052B2 Version pressure feedback mechanisms for speculative versioning caches 失效
标题翻译：针对推测版本控制缓存的版本压力反馈机制
公开(公告)号：US08397052B2
公开(公告)日：2013-03-12
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

39. 发明申请

US20110172968A1 DISTRIBUTED PERFORMANCE COUNTERS 失效
标题翻译：分布式性能计数器
公开(公告)号：US20110172968A1
公开(公告)日：2011-07-14
申请号：US12684738
申请日：2010-01-08
申请人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
发明人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
IPC分类号： G21C17/00
CPC分类号： G06F13/4247 , G06F9/30145 , G06F11/3476 , G06F11/348 , G06F11/3495 , G06F12/0897 , G06F2201/88 , G06F2221/2117
摘要： A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
摘要翻译：多个第一性能计数器模块耦合到多个处理核心。多个第一性能计数器模块可操作以分别收集与多个处理核心相关联的性能数据。多个第二性能计数器模块耦合到多个L2高速缓存单元，并且所述多个第二性能计数器模块可操作以分别收集与所述多个L2高速缓存单元相关联的性能数据。中央性能计数器模块可以用于协调来自多个第一性能计数器模块和多个第二性能模块的计数器数据，中央性能计数器模块，多个第一性能计数器模块和多个第二性能计数器模块通过菊花链连接连接。

40. 发明申请

US20050081078A1 Deterministic error recovery protocol 失效
标题翻译：确定性错误恢复协议
公开(公告)号：US20050081078A1
公开(公告)日：2005-04-14
申请号：US10674952
申请日：2003-09-30
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , H04L29/06 , H04L29/14
CPC分类号： G06F11/1443 , G06F11/0709 , G06F11/0793 , H04L1/0052 , H04L69/28 , H04L69/40 , H04L2001/0092
摘要： Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.
摘要翻译：公开了一种用于与具有第一和第二节点的通信系统一起使用的错误恢复方法和系统，每个所述节点具有接收器和发送器，第一节点的发送器通过第一电缆连接到第二节点的接收器并且第二节点的发送者通过第二电缆连接到第一节点的接收器。所述方法包括在所述节点中的一个检测到错误之后的两个节点进入相同的定义状态的步骤。特别地，第一节点的接收机进入错误状态，在定义的时间段T内保持在错误状态，并且在所述定义的时间段T之后进入等待状态。此外，第一节点的发送方在给定的时间段Te的情况下向第二节点的接收者发送错误消息，并且在定义的时间段Te之后，第一节点的发送者进入空闲状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式