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31. 发明授权

US08742503B2 Recessed single crystalline source and drain for semiconductor-on-insulator devices 有权
标题翻译：用于绝缘体上半导体器件的嵌入式单晶源极和漏极
公开(公告)号：US08742503B2
公开(公告)日：2014-06-03
申请号：US13285162
申请日：2011-10-31
申请人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
发明人： Geng Wang , Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/84 , H01L27/1203
摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.
摘要翻译：在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部，衬底，从而形成源极沟槽和漏极沟槽。在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于顶部半导体层的厚度。

32. 发明申请

US20130181326A1 MULTILAYER MIM CAPACITOR 有权
公开(公告)号：US20130181326A1
公开(公告)日：2013-07-18
申请号：US13352655
申请日：2012-01-18
申请人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Kangguo Cheng , Joseph Ervin , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/92 , H01L21/02 , B82Y99/00
CPC分类号： H01L28/40 , H01L21/32134 , H01L28/86 , H01L28/90 , H01L28/91
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

33. 发明申请

US20100032732A1 ELECTRICAL ANTIFUSE HAVING A MULTI-THICKNESS DIELECTRIC LAYER 有权
标题翻译：具有多层电介质层的电抗体
公开(公告)号：US20100032732A1
公开(公告)日：2010-02-11
申请号：US12187003
申请日：2008-08-06
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
IPC分类号： H01L29/78 , H01L21/336 , H01L23/525
CPC分类号： H01L23/5252 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
摘要翻译：包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程电极，即晶体管的主体和栅电极，跨过栅极电介质。

34. 发明授权

US07825479B2 Electrical antifuse having a multi-thickness dielectric layer 有权
标题翻译：具有多层电介质层的电反熔丝
公开(公告)号：US07825479B2
公开(公告)日：2010-11-02
申请号：US12187003
申请日：2008-08-06
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/5252 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
摘要翻译：包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程电极，即晶体管的主体和栅电极，跨过栅极电介质。

35. 发明申请

US20100200949A1 METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE 审中-公开
标题翻译：用于调节金属栅极和高K器件的阈值电压的方法
公开(公告)号：US20100200949A1
公开(公告)日：2010-08-12
申请号：US12370024
申请日：2009-02-12
申请人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L27/0605 , H01L27/0733 , H01L27/1203 , H01L28/90 , H01L29/66181
摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.
摘要翻译：形成深沟槽电容器的方法包括提供晶片。器件形成在晶片的前侧。在晶片的基板上形成贯通硅通孔。深沟槽形成在晶片的背面。在深沟槽中形成深沟槽电容器。直通硅通孔将深沟槽电容器连接到器件。

36. 发明授权

US08455979B2 Three dimensional integrated deep trench decoupling capacitors 失效
标题翻译：三维集成深沟槽去耦电容器
公开(公告)号：US08455979B2
公开(公告)日：2013-06-04
申请号：US13369460
申请日：2012-02-09
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

37. 发明授权

US08921198B2 Method and structure for forming a deep trench capacitor 有权
标题翻译：形成深沟槽电容器的方法和结构
公开(公告)号：US08921198B2
公开(公告)日：2014-12-30
申请号：US13428303
申请日：2012-03-23
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/02 , H01L29/66 , H01L29/94 , H01L27/07 , H01L27/12 , H01L49/02 , H01L27/06
CPC分类号： H01L29/945 , H01L27/0605 , H01L27/0733 , H01L27/1203 , H01L28/90 , H01L29/66181
摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.
摘要翻译：形成深沟槽电容器的方法包括提供晶片。器件形成在晶片的前侧。在晶片的基板上形成贯通硅通孔。深沟槽形成在晶片的背面。在深沟槽中形成深沟槽电容器。直通硅通孔将深沟槽电容器连接到器件。

38. 发明申请

US20120133023A1 THREE DIMENSIONAL INTEGRATED DEEP TRENCH DECOUPLING CAPACITORS 失效
标题翻译：三维集成深层解压电容器
公开(公告)号：US20120133023A1
公开(公告)日：2012-05-31
申请号：US13369460
申请日：2012-02-09
申请人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/92
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

39. 发明授权

US08222104B2 Three dimensional integrated deep trench decoupling capacitors 有权
标题翻译：三维集成深沟槽去耦电容器
公开(公告)号：US08222104B2
公开(公告)日：2012-07-17
申请号：US12509780
申请日：2009-07-27
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

40. 发明申请

US20110018095A1 THREE DIMENSIONAL INTEGRATED DEEP TRENCH DECOUPLING CAPACITORS 有权
标题翻译：三维集成深层解压电容器
公开(公告)号：US20110018095A1
公开(公告)日：2011-01-27
申请号：US12509780
申请日：2009-07-27
申请人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

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