专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20050196929A1 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US20050196929A1
公开(公告)日：2005-09-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻凸起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

32. 发明授权

US06221789B1 Thin oxides of silicon 失效
标题翻译：硅的薄氧化物
公开(公告)号：US06221789B1
公开(公告)日：2001-04-24
申请号：US09124562
申请日：1998-07-29
申请人： Reza Arghavani , Robert S. Chau
发明人： Reza Arghavani , Robert S. Chau
IPC分类号： H01L21469
CPC分类号： H01L21/28211 , C23C8/10 , H01L21/02238 , H01L21/02255 , H01L21/3144 , H01L21/31654 , H01L21/31662
摘要： An oxidation process that produces multi-layer, yet very thin oxides of silicon, formed on silicon substrates, includes pushing wafers at a particular range of speeds, into a furnace at a particular range of temperatures, sequentially oxidizing the wafers in varying chemical ambients, and operating an external chlorine compound generator coupled to the furnace. Oxides formed in this manner have good uniformity and low interface state density and are suitable for forming FETs. In a particular embodiment, a first portion of an oxide stack is formed in an oxygen/nitrogen ambient, a second portion of an oxide stack is formed in a carbon dioxide/hydrogen chloride/oxygen ambient, and a third portion of an oxide stack is formed by a wet oxidation. The second portion of the oxide stack is formed when 1,2-dichloroethylene is treated with heat and oxygen to produce carbon dioxide and hydrogen chloride gas that is then introduced into the furnace.
摘要翻译：在硅衬底上形成多层但非常薄的硅氧化物的氧化工艺包括将晶片以特定的速度推入特定温度范围内的炉中，在不同的化学环境中依次氧化晶片，并操作耦合到炉的外部氯化合物发生器。以这种方式形成的氧化物具有良好的均匀性和低界面态密度，并且适于形成FET。在一个具体实施方案中，在氧/氮环境中形成氧化物堆叠的第一部分，形成氧化物堆叠的第二部分在二氧化碳/氯化氢/氧气环境中，并且氧化物堆叠的第三部分通过湿氧化形成。当用热和氧处理1,2-二氯乙烯时，形成氧化物堆叠的第二部分，以产生二氧化碳和氯化氢气体，然后将其引入炉中。

33. 发明授权

US6153480A Advanced trench sidewall oxide for shallow trench technology 有权
标题翻译：先进的沟槽侧壁氧化物用于浅沟槽技术
公开(公告)号：US6153480A
公开(公告)日：2000-11-28
申请号：US164112
申请日：1998-09-30
申请人： Reza Arghavani , Robert S Chau , Binny Arcot
发明人： Reza Arghavani , Robert S Chau , Binny Arcot
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76235
摘要： A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. The trench is subjected to a nitrogen-oxide gas ambient and is annealed to form a silicon-oxynitride surface along the trench sidewalls. A first oxide layer is then formed within the trench. The first oxide layer is subjected to a nitridation step and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention reduce dopant outdiffusion, reduce trench stresses, allow more uniform growth of thin gate oxides, and permit the use of thinner gate oxides.
摘要翻译：描述在半导体衬底中形成隔离结构的方法。首先将沟槽蚀刻到半导体衬底中。将沟槽经受氮氧化物气体环境并退火以形成沿沟槽侧壁的氧氮化硅表面。然后在沟槽内形成第一氧化物层。对第一氧化物层进行氮化步骤，并在第一氧化物层和第一氧化物层与半导体衬底之间的氧氮化物界面上进行退火以形成氧氮化物表面。然后将第二氧化物层沉积在第一氧化物层的氧化氮化物表面上。本发明的方法和隔离结构减少掺杂剂扩散，减小沟槽应力，允许薄栅氧化物的更均匀生长，并允许使用更薄的栅极氧化物。

34. 发明申请

US20140308812A1 CVD BASED METAL/SEMICONDUCTOR OHMIC CONTACT FOR HIGH VOLUME MANUFACTURING APPLICATIONS 有权
标题翻译：基于CVD的金属/半导体OHMIC联系人用于高容量制造应用
公开(公告)号：US20140308812A1
公开(公告)日：2014-10-16
申请号：US13862048
申请日：2013-04-12
申请人： Reza Arghavani , Jeffrey Marks , Benjamin A. Bonner
发明人： Reza Arghavani , Jeffrey Marks , Benjamin A. Bonner
IPC分类号： H01L21/768 , H01L21/67
CPC分类号： H01L21/7688 , H01L21/285 , H01L21/76831 , H01L21/76834 , H01L23/485 , H01L29/0895 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for manufacturing an interconnect structure to provide ohmic contact in a semiconductor device is provided. The method includes providing a semiconductor device, such as a transistor, comprising a substrate, a gate dielectric, a gate electrode, and source and drain regions in the substrate. An ultra-thin interfacial dielectric is deposited by chemical vapor deposition (CVD) over the source and drain regions, where the interfacial dielectric can have a thickness between about 3 Å and about 20 Å. The ultra-thin interfacial dielectric is configured to unpin the metal Fermi level from the source and drain regions. Other steps such as the deposition of a metal by CVD and the cleaning of the substrate surface can be performed in an integrated process tool without a vacuum break. The method further includes forming one or more vias through a pre-metal dielectric over the source and drain regions of the substrate.
摘要翻译：提供一种用于制造在半导体器件中提供欧姆接触的互连结构的装置和方法。该方法包括在衬底中提供诸如晶体管的半导体器件，其包括衬底，栅极电介质，栅极电极以及源极和漏极区域。通过在源极和漏极区域上的化学气相沉积（CVD）沉积超薄界面电介质，其中界面电介质可以具有在约和之间的厚度。超薄界面电介质被配置为从源极和漏极区域去除金属费米能级。其他步骤，例如通过CVD沉积金属和清洁基板表面可以在没有真空断裂的集成工艺工具中进行。该方法还包括在衬底的源极和漏极区域上形成通过前金属电介质的一个或多个通孔。

35. 发明授权

US08501568B2 Method of forming flash memory with ultraviolet treatment 失效
标题翻译：用紫外线处理形成闪存的方法
公开(公告)号：US08501568B2
公开(公告)日：2013-08-06
申请号：US12256173
申请日：2008-10-22
申请人： Mihaela Balseanu , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
发明人： Mihaela Balseanu , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
IPC分类号： H01L21/326 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/00 , H01L29/792
CPC分类号： H01L21/3185 , H01L21/28282 , H01L21/3105 , H01L21/3115 , H01L21/31155 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
摘要翻译：提供了形成闪速存储器件的方法。闪存器件包括在衬底上的二氧化硅层和形成在二氧化硅层上的氮化硅层。氮化硅层的性质可以通过以下任何方式改变：将氮化硅层暴露于紫外线辐射，将氮化硅层暴露于电子束，以及通过等离子体处理氮化硅层。介电材料沉积在氮化硅层上，并且在电介质材料上形成导电日期。具有改进的氮化硅层的闪速存储器件提供了非易失性存储器件的单元电池的电荷保持容量和电荷保持时间的增加。

36. 发明申请

US20110309447A1 TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF 有权
标题翻译：具有阈值电压设置的晶体管及其制造方法
公开(公告)号：US20110309447A1
公开(公告)日：2011-12-22
申请号：US12971955
申请日：2010-12-17
申请人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
发明人： Reza Arghavani , Pushkar Ranade , Lucian Shifren , Scott E. Thompson , Catherine de Villeneuve
IPC分类号： H01L27/088 , H01L21/76
CPC分类号： H01L27/0921 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/823892 , H01L27/088 , H01L27/092 , H01L29/0653 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/365 , H01L29/4966 , H01L29/66537 , H01L29/6659 , H01L29/7833 , H01L29/7836
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.
摘要翻译：其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。结果是能够独立地控制VT（具有低电平（VT））和VDD（VDD），从而使给定器件的体偏压可以与VT分开调谐。

37. 发明申请

US20100096687A1 NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER 有权
标题翻译：非易失性存储器，含有硝酸盐电荷捕获层
公开(公告)号：US20100096687A1
公开(公告)日：2010-04-22
申请号：US12255617
申请日：2008-10-21
申请人： Mihaela BALSEANU , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
发明人： Mihaela BALSEANU , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/31
CPC分类号： H01L21/3185 , H01L21/28282 , H01L21/3105 , H01L21/3115 , H01L21/31155 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
摘要翻译：提供闪速存储器件和形成闪存器件的方法。闪速存储器件包括具有包含碳，硼或氧的掺杂剂的掺杂氮化硅层。掺杂的氮化硅层在该层中产生更高数量和更高浓度的氮和硅悬挂键，并且提供了非易失性存储器件的单元电池的电荷保持容量和电荷保留时间的增加。

38. 发明申请

US20090087977A1 LOW TEMPERATURE CONFORMAL OXIDE FORMATION AND APPLICATIONS 有权
标题翻译：低温一致性氧化物形成与应用
公开(公告)号：US20090087977A1
公开(公告)日：2009-04-02
申请号：US12241826
申请日：2008-09-30
申请人： MATTHEW SPULLER , Melody Agustin , Meiyee (Maggie Le) Shek , Li-Qun Xia , Reza Arghavani
发明人： MATTHEW SPULLER , Melody Agustin , Meiyee (Maggie Le) Shek , Li-Qun Xia , Reza Arghavani
IPC分类号： H01L21/3205
CPC分类号： H01L21/31608 , C23C16/0272 , H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L27/11519 , H01L27/11521 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.
摘要翻译：本发明总体上提供了用于处理半导体衬底的装置和方法。特别地，本发明的实施例涉及一种用于形成半导体器件的方法和装置，其具有在低温下形成的共形氧化硅层。本发明的一个实施例提供一种形成半导体栅极结构的方法。该方法包括在半导体衬底上形成栅叠层，在半导体衬底上使用低温循环法形成共形氧化硅层，并在保形氧化硅层上形成间隔层。

39. 发明申请

US20080061285A1 Metal layer inducing strain in silicon 审中-公开
标题翻译：金属层在硅中诱导应变
公开(公告)号：US20080061285A1
公开(公告)日：2008-03-13
申请号：US11490884
申请日：2006-07-21
申请人： Reza Arghavani , Jianming Fu
发明人： Reza Arghavani , Jianming Fu
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/7833 , H01L29/7845
摘要： A metal layer, especially a metal compound, induces strain into a gate channel of a MOS transistor. Compressive strain of over 4 GPa is available from sputter deposited TiN. The amount of strain can be controlled at least up to 11 GPa, for example, by wafer biasing. The compressive strain may induce compressive strain in a PMOS channel when deposited around the channel and induce tensile strain in an NMOS channel when deposited over the channel.
摘要翻译：金属层，特别是金属化合物，在MOS晶体管的栅极沟道中引起应变。超过4 GPa的压缩应变可从溅射沉积的TiN获得。可以通过例如晶片偏置将应变量控制在至少高达11GPa。当沉积在通道周围时，压缩应变可能在PMOS沟道中引起压缩应变，并且当沉积在沟道上时，在NMOS沟道中引起拉伸应变。

40. 发明授权

US07087497B2 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US07087497B2
公开(公告)日：2006-08-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻隆起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式