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31. 发明授权

US6035390A Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation 失效
标题翻译：用于与执行算术或逻辑运算同时产生和逻辑组合小于（LT），大于（GT）和等于（EQ））条件码位的方法和装置
公开(公告)号：US6035390A
公开(公告)日：2000-03-07
申请号：US5471
申请日：1998-01-12
申请人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
发明人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F9/38 , G06F7/48 , G06F9/302 , G06F9/305 , G06F9/32 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/48 , G06F9/30094
摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.
摘要翻译：处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位的执行单元的指令。在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。

32. 发明授权

US6014763A At-speed scan testing 失效
标题翻译：高速扫描测试
公开(公告)号：US6014763A
公开(公告)日：2000-01-11
申请号：US7670
申请日：1998-01-15
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
摘要翻译：通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换，从集成电路并行扫描输出到测试仪。通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。对于超过1 GHz的速度，可以实现高速扫描测试。

33. 发明授权

US5964827A High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US5964827A
公开(公告)日：1999-10-12
申请号：US971653
申请日：1997-11-17
申请人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
发明人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F7/50 , G06F7/508 , G06F7/52
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个四位组生成电路和多个四位组传播电路。四位组生成电路中的每一个产生相应位位置的生成信号。四位组传播电路中的每一个产生用于相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

34. 发明授权

US06574698B1 Method and system for accessing a cache memory within a data processing system 失效
标题翻译：用于访问数据处理系统内的高速缓冲存储器的方法和系统
公开(公告)号：US06574698B1
公开(公告)日：2003-06-03
申请号：US09062002
申请日：1998-04-17
申请人： Sang Hoo Dhong , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A method for accessing a cache memory within a data processing system is disclosed. The cache memory includes a memory array and a directory along with a translation lookaside buffer. The cache memory may be accessed by an effective address that includes a byte field, a line field, and an effective page number field. In order to facilitate the cache access process, a translation array is provided that has the same number of rows as the translation lookaside buffer. Each row of the translation array has the same number of array entries as the product of the number of lines per page of a system memory and the set associativity of the cache. The translation array is updated after the contents of the directory or the translation lookaside buffer have been updated. The translation array can be accessed with the contents of a line field of an effective address to determine whether or not the cache memory stores data associated with translated address.
摘要翻译：公开了一种用于访问数据处理系统内的高速缓冲存储器的方法。缓存存储器包括存储器阵列和目录以及翻译后备缓冲器。高速缓冲存储器可以由包括字节字段，行字段和有效页号字段的有效地址来访问。为了便于缓存访问过程，提供了具有与翻译后备缓冲器相同数量的行的翻译数组。翻译数组的每一行具有与系统存储器每页的行数和缓存的集合关联性的乘积相同的数组条目数。在更新目录或翻译后备缓冲区的内容之后更新翻译数组。可以使用有效地址的行字段的内容来访问翻译数组，以确定高速缓冲存储器是否存储与翻译的地址相关联的数据。

35. 发明授权

US06393446B1 32-bit and 64-bit dual mode rotator 失效
标题翻译： 32位和64位双模旋转器
公开(公告)号：US06393446B1
公开(公告)日：2002-05-21
申请号：US09343450
申请日：1999-06-30
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Joel Abraham Silberman
IPC分类号： G06F700
CPC分类号： G06F7/762 , G06F5/015
摘要： A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.
摘要翻译：能够执行32位和64位旋转的双模旋转器。根据优选实施例，双模旋转器包括第一，第二和第三旋转单元，其中每个旋转器具有多个输入和输出。第二旋转器的输入可操作地连接到第一旋转单元的相应输出端。第三旋转单元的输入可操作地连接到第二旋转器的相应输出。响应于选择32位旋转模式，第一旋转器的输入的上半部分为零，并且第三旋转器的输出的下半部分被复制在第三旋转器的输出的上半部分中。

36. 发明授权

US06239620B1 Method and apparatus for generating true/complement signals 失效
标题翻译：用于产生真/补补信号的方法和装置
公开(公告)号：US06239620B1
公开(公告)日：2001-05-29
申请号：US09450982
申请日：1999-11-29
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： H03K33568
CPC分类号： H03K5/151
摘要： A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.
摘要翻译：公开了一种具有动态节点的动态逻辑电路的真/补信号发生器。具有动态节点的动态逻辑电路的真/补信号发生器包括级联反相器电路，第一半锁存电路和第二半锁存电路。连接到动态节点的级联逆变器电路包括与第二反相器串联连接的第一反相器。连接到级联逆变器电路的第二反相器的输出端，第一半锁存电路产生输出信号。连接到级联逆变器电路的第一反相器的输出端，第二半锁存电路产生补码输出信号。

37. 发明授权

US06226731B1 Method and system for accessing a cache memory within a data-processing system utilizing a pre-calculated comparison array 失效
标题翻译：使用预先计算的比较阵列访问数据处理系统内的高速缓冲存储器的方法和系统
公开(公告)号：US06226731B1
公开(公告)日：2001-05-01
申请号：US09149229
申请日：1998-09-08
申请人： Sang Hoo Dhong , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A cache memory within a data processing system. The cache memory includes a number of cache lines over which data may be transferred. The cache memory also includes a translation lookaside buffer for associating real addresses with virtual addresses. Virtual segment identifiers are stored within the translation lookaside buffer. In addition, the cache memory includes a comparison array for cross referencing virtual segment identifiers with effective addresses. The comparison array includes spaces populated with indications of whether or not a particular virtual segment identifier maintained within the translation lookaside buffer corresponds to a particular effective address. The comparison array allows a comparison to be performed in advance between effective addresses within the cache memory and all possible virtual segment identifiers maintained in the translation lookaside buffer prior to any conversion of virtual addresses to real addresses. In addition, each virtual segment identifier is composed of a portion of a virtual address.
摘要翻译：数据处理系统内的高速缓冲存储器。高速缓存存储器包括可以传送数据的多条高速缓存行。高速缓冲存储器还包括用于将实际地址与虚拟地址相关联的翻译后备缓冲器。虚拟段标识符存储在翻译后备缓冲区中。此外，高速缓存存储器包括用于交叉引用具有有效地址的虚拟段标识符的比较阵列。比较阵列包括填充有维持在翻译后备缓冲器内的特定虚拟段标识符是否对应于特定有效地址的指示的空间。比较阵列允许在将虚拟地址转换为实际地址之前，在高速缓冲存储器内的有效地址和保持在转换后备缓冲器中的所有可能的虚拟段标识符之间进行比较。此外，每个虚拟段标识符由虚拟地址的一部分组成。

38. 发明授权

US6161164A Content addressable memory accessed by the sum of two operands 失效
标题翻译：内容可寻址存储器由两个操作数的总和访问
公开(公告)号：US6161164A
公开(公告)日：2000-12-12
申请号：US716817
申请日：1996-09-16
申请人： Sang Hoo Dhong , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F12/10 , G11C15/00 , G06F12/00 , G06F7/00
CPC分类号： G11C15/00 , G06F12/1027
摘要： Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory. Two inputs to the content-addressable memory are conditioned and then supplied to matching cells, which determine which address stored in the content-addressable memory will be output. This is accomplished without a full adder being implemented to add the two input operands before being supplied to the content-addressable memory.
摘要翻译：在内容可寻址存储器中，通过组合在内容可寻址存储器内的有效地址生成添加和搜索的步骤来减少存储器访问中的延迟。对内容可寻址存储器的两个输入进行调节，然后提供给匹配的单元，这些单元确定存储在内容可寻址存储器中的地址将被输出。这是在没有实现全加器以在将两个输入操作数提供给内容可寻址存储器之前实现的。

39. 发明授权

US06914453B2 Integrated logic and latch design with clock gating at static input signals 失效
标题翻译：具有静态输入信号时钟门控的集成逻辑和锁存器设计
公开(公告)号：US06914453B2
公开(公告)日：2005-07-05
申请号：US10616850
申请日：2003-07-10
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Joel Abraham Silberman , Naoka Yano
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A method and an apparatus are provided for implementing a logic circuit with integrated logic and latch design. A clock input is provided to the logic circuit. One or more static signal inputs are further provided to the logic circuit. One or more dynamic signal inputs are generated by dynamically gating the one or more static signal inputs with the clock signal. The one or more dynamic signal inputs are applied to the logic circuit, and one or more dynamic signal outputs of the logic circuit are generated. The one or more dynamic signal outputs are precharged, and the one or more dynamic signal outputs are evaluated. The one or more dynamic signal outputs are held when the one or more dynamic signal outputs are neither being precharged nor being evaluated. The one or more dynamic signal outputs are converted into one or more static signal outputs.
摘要翻译：提供了一种用于实现具有集成逻辑和锁存器设计的逻辑电路的方法和装置。时钟输入提供给逻辑电路。一个或多个静态信号输入进一步提供给逻辑电路。通过用时钟信号动态选通一个或多个静态信号输入来产生一个或多个动态信号输入。一个或多个动态信号输入被施加到逻辑电路，并且产生逻辑电路的一个或多个动态信号输出。一个或多个动态信号输出被预充电，并且评估一个或多个动态信号输出。当一个或多个动态信号输出既不被预充电也不被评估时，一个或多个动态信号输出被保持。一个或多个动态信号输出被转换成一个或多个静态信号输出。

40. 发明授权

US06453390B1 Processor cycle time independent pipeline cache and method for pipelining data from a cache 有权
标题翻译：处理器周期时间独立的流水线缓存和从缓存流水线数据的方法
公开(公告)号：US06453390B1
公开(公告)日：2002-09-17
申请号：US09458405
申请日：1999-12-10
申请人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
发明人： Naoaki Aoki , Sang Hoo Dhong , Nobuo Kojima , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0859 , G06F12/0893
摘要： A processor cycle time independent pipeline cache and method for pipelining data from a cache provide a processor with operand data and instructions without introducing additional latency for synchronization when processor frequency is lowered or when a reload port provides a value a cycle earlier than a read access from the cache storage. The cache incorporates a persistent data bus that synchronizes the stored data access with the pipeline and can also utilize bypass mode data available from a cache input from the lower level when data is being written to the cache.
摘要翻译：处理器周期时间独立的流水线高速缓存和用于从高速缓存流水线提供数据的方法为处理器提供操作数数据和指令，而不会在处理器频率降低时引入额外的同步延迟，或者当重新加载端口提供比读取访问更早的值时缓存存储。高速缓存包括持久性数据总线，其将存储的数据访问与流水线同步，并且当数据被写入高速缓存时，还可以使用从较低级别的高速缓存输入中可用的旁路模式数据。

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