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31. 发明授权

US06661057B1 Tri-level segmented control transistor and fabrication method 失效
标题翻译：三电平分段控制晶体管及其制造方法
公开(公告)号：US06661057B1
公开(公告)日：2003-12-09
申请号：US09056836
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L27088
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/32053 , H01L21/76802 , H01L21/76855 , H01L29/66484 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7833 , Y10S257/90
摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
摘要翻译：晶体管形成在具有分段栅极结构的有源区中。分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。这些间隔物通过绝缘层与栅电极电隔离。形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

32. 发明授权

US06410409B1 Implanted barrier layer for retarding upward diffusion of substrate dopant 失效
标题翻译：用于延缓衬底掺杂剂的向上扩散的植入阻挡层
公开(公告)号：US06410409B1
公开(公告)日：2002-06-25
申请号：US08741799
申请日：1996-10-31
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21265
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/26513 , H01L21/74
摘要： Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.
摘要翻译：在随后的热处理操作（例如退火）期间，在半导体衬底内形成深P +层的硼向上扩散。用于延迟硼的这种向上扩散的方法包括注入氮以在P +层的上边界附近形成氮阻挡层，并且远低于晶体管源/漏区。一个实施例包括形成在下面的P +衬底上的轻掺杂的外延层。在另一个实施例中，深硼注入在P-衬底内形成P +层，并提供外延层的许多优点，而不需要这样的外延层。以1-3MeV的优选能量进行氮注入，以在1-5微米范围内的深度形成注入的氮阻挡层。氧也可以被植入以形成扩散阻挡层，以阻止形成深N +层的砷或磷的向上扩散。

33. 发明授权

US06380055B2 Dopant diffusion-retarding barrier region formed within polysilicon gate layer 有权
标题翻译：在多晶硅栅极层内形成的掺杂扩散阻滞层
公开(公告)号：US06380055B2
公开(公告)日：2002-04-30
申请号：US09177043
申请日：1998-10-22
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L213205
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/32155
摘要： A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.
摘要翻译：扩散阻滞屏障区域被结合到栅电极中以减少掺杂剂朝向栅极电介质的向下扩散。阻挡区域是在两个单独形成的多晶硅层之间形成的含氮扩散阻滞区域。多晶硅的上层比多晶硅的下层掺杂更多，并且势垒区域用于将大部分掺杂剂保持在多晶硅的上层内，并且还可以允许一些掺杂剂扩散到多晶硅的下层。阻挡区域可以例如通过在含氮环境中退火第一多晶硅层以在第一多晶硅层的顶表面处形成氮化层而形成。可以通过在第一多晶硅层的顶表面上沉积含氮层，例如氮化硅或氮化钛层来形成阻挡区。含氮层的厚度优选为约5〜约厚。驻留在栅极电介质顶部的任何氮可以保持在小于约2％的浓度。当使用诸如硼的p型掺杂剂时，本发明特别适用于薄栅极电介质，例如厚度大约为25埃的那些。

34. 发明授权

US06225151B1 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion 失效
标题翻译：晶体管源极/漏极区域之下的氮衬垫以延迟掺杂剂扩散
公开(公告)号：US06225151B1
公开(公告)日：2001-05-01
申请号：US08871469
申请日：1997-06-09
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2122
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28176 , H01L21/28202 , H01L21/823814 , H01L29/1033 , H01L29/518 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7833
摘要： A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.
摘要翻译：基本上在IGFET的源极/漏极区域下方大致相邻地形成的氮注入区域形成衬垫，以在随后的热处理操作（例如退火步骤）期间阻止源极/漏极掺杂剂原子的扩散。可以在将源极/漏极掺杂剂注入较低深度之前通过将氮注入给定深度来形成氮衬垫。也可以将氮气引入到栅电极下面的IGFET沟道区域的区域中，以阻止源极/漏极掺杂剂的随后的横向扩散。可以使用一个或多个成角度的注入步骤来实现这种氮引入，或者可以通过使用与栅电极对准的垂直注入形成的注入氮层退火来实现。衬垫可以形成在IGFET的漏极侧或源极和漏极两侧，并且可以形成在漏极和/或源极的重掺杂区域的轻掺杂区域下方。这种衬垫对于硼掺杂的源极/漏极区域是特别有利的，并且可以与没有这样的衬垫形成的N沟道IGFET组合。

35. 发明授权

US06197645B1 Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls 失效
标题翻译：制造具有较高的源极/漏极区域的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US06197645B1
公开(公告)日：2001-03-06
申请号：US08837539
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/41775 , H01L29/41783 , H01L29/42376
摘要： An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer. The method also includes implanting a dopant into the elevated source and drain regions, and diffusing the dopant from the elevated source and drain regions into the underlying source and drain regions. Preferably, the semiconducting layer is deposited by epitaxial deposition, the lower gate level is substantially thicker than the semiconducting layer, the elevated source and drain regions include sidewalls beneath and substantially aligned with sidewalls of the upper gate level, and all source/drain doping in the underlying source and drain regions is diffused from the elevated source and drain regions. In this manner, a highly miniaturized IGFET can be provided with shallow channel junctions without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了一种IGFET，其具有与具有倾斜侧壁的栅极紧密相邻的源极和漏极区域。制造IGFET的方法包括在半导体衬底上形成较低的栅极电平，其中下部栅极级别包括顶部表面，底部表面和倾斜的相对侧壁，并且顶部表面具有比底部表面大得多的长度，以及在半导体衬底的下栅极电平和下面的源极和漏极区域上沉积半导体层以在下部栅极电平上形成上部栅极电平，在下部源极区域上形成升高的源极区域，以及在下部栅极漏区。由于下栅极电平的侧壁的逆向斜率，升高的源极和漏极区域与下部栅极电平分离，并且由于在栅极栅极电平上缺乏阶跃覆盖，升高的源极和漏极区域与上部栅极电平分离半导体层。该方法还包括将掺杂剂注入到升高的源极和漏极区域中，并且将掺杂剂从升高的源极和漏极区域扩散到下面的源极和漏极区域中。优选地，半导体层通过外延沉积沉积，下栅极电平基本上比半导电层更厚，升高的源极和漏极区域包括在上部栅极电平的侧壁下面并基本对齐的侧壁，并且所有源极/漏极掺杂底层源极和漏极区域从升高的源极和漏极区域扩散。以这种方式，高度小型化的IGFET可以设置有浅沟道结，而不需要邻近门的侧壁间隔。

36. 发明授权

US5918129A Method of channel doping using diffusion from implanted polysilicon 失效
标题翻译：使用注入多晶硅扩散的沟道掺杂方法
公开(公告)号：US5918129A
公开(公告)日：1999-06-29
申请号：US806562
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/225 , H01L29/10 , H01L21/336
CPC分类号： H01L29/1033 , H01L21/2256
摘要： A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the isolation structure, depositing a polysilicon blanket layer overlying the thin oxide layer, patterning a photoresist mask overlying the polysilicon blanket layer and implanting dopant impurities into the polysilicon blanket layer. The method further includes steps of diffusing the dopant impurities from the polysilicon blanket layer through the thin oxide layer into the integrated circuit device channel, removing the polysilicon blanket layer, and removing the thin oxide layer.
摘要翻译：公开了一种在由隔离结构横向封闭的半导体衬底中掺杂集成电路器件沟道的方法。该方法包括以下步骤：形成覆盖集成电路器件沟道和隔离结构的薄氧化物层，沉积覆盖薄氧化物层的多晶硅覆盖层，图案化覆盖多晶硅覆盖层的光刻胶掩模，并将掺杂杂质注入多晶硅覆盖层。该方法还包括以下步骤：将来自多晶硅覆盖层的掺杂剂杂质通过薄氧化物层扩散到集成电路器件沟道中，去除多晶硅覆盖层，以及去除薄氧化物层。

37. 发明授权

US5837557A Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern 失效
标题翻译：形成主层以组合电路图案的单独打印块的半导体制造方法
公开(公告)号：US5837557A
公开(公告)日：1998-11-17
申请号：US818478
申请日：1997-03-14
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/78 , H01L21/82
CPC分类号： H01L21/0274 , H01L21/76838 , H01L21/76895 , H01L21/823871
摘要： Each circuit block of a plurality of circuit blocks on a semiconductor substrate is imaged in an exposure field defined by a reticle. The circuit blocks are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The circuit blocks are globally interconnected by depositing a blanket metal layer, masking the metal layer and etching the metal layer using a stitching reticle having an exposure field overlapping the plurality of circuit blocks. The combination of reticle-imaged circuit blocks allows each individual circuit block to be fabricated independently, using independent imaging resolution, layout rules, design rules, different polysilicon sizes and source/drain region sizes and the like. In addition different reticles, including different reticle types, resolutions and qualities may be used to construct the various circuit blocks. Different imaging technologies may be used to construct the independent circuit blocks, including X-ray, I-line, H-line, ion-beam and electron-beam irradiation, for example. While the different circuit blocks are independently constructed, the circuit blocks are globally interconnected using the blanket metal layer so that overall circuit size is reduced, circuit quality is enhanced, fabrication time and costs are reduced, and performance is increased. A plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are globally interconnected using a blanket metal layer that is imaged using a stitch mask and etch operation that combines and electrically connects the individual integrated chips.
摘要翻译：在半导体衬底上的多个电路块的每个电路块在由光罩定义的曝光场中成像。电路块通过诸如场氧化物或沟槽隔离的隔离在半导体衬底内分离和电隔离。电路块通过沉积橡皮布金属层，掩蔽金属层和使用具有与多个电路块重叠的曝光场的缝合掩模版蚀刻金属层而全局互连。标线片成像电路块的组合允许使用独立的成像分辨率，布局规则，设计规则，不同的多晶硅尺寸和源极/漏极区域尺寸等来独立地制造每个单独的电路块。此外，可以使用不同的标线片，包括不同的标线片类型，分辨率和质量来构造各种电路块。例如，可以使用不同的成像技术来构建独立的电路块，包括X射线，I线，H线，离子束和电子束照射。虽然不同的电路块是独立构造的，但电路块使用橡皮布金属层进行全局互连，从而减小了整体电路尺寸，提高了电路质量，降低了制造时间和成本，并提高了性能。使用多个集成芯片组中的每一个的单独的掩模版成像，在单个半导体晶片上构造包括微处理器，存储器和支持芯片的多个集成芯片组。不同的电路通过使用缝合掩模成像的覆盖金属层和组合并电连接各个集成芯片的蚀刻操作来全局互连。

38. 发明授权

US5827761A Method of making NMOS and devices with sequentially formed gates having different gate lengths 失效
标题翻译：制造具有不同栅极长度的具有顺序形成的栅极的NMOS和器件的方法
公开(公告)号：US5827761A
公开(公告)日：1998-10-27
申请号：US805537
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385
摘要： A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the second active region, wherein the first and second gates are formed in sequence and have different lengths, and forming a source and drain in the first active region and a source and drain in the second active region. Preferably, the first gate is defined by a first photoresist layer patterned with a first exposure time, the second gate is defined by a second photoresist layer patterned with a second exposure time, and the difference in gate lengths is due primarily to a difference between the first and second exposure times.
摘要翻译：制造具有不同栅极长度的NMOS和PMOS器件的方法包括：提供具有第一和第二有源区的半导体衬底，在第一有源区的一部分上形成第一栅极，在第二有源区的一部分上形成第二栅极，其中第一和第二栅极依次形成并且具有不同的长度，并且在第一有源区中形成源极和漏极以及在第二有源区中形成源极和漏极。优选地，第一栅极由以第一曝光时间图案化的第一光致抗蚀剂层限定，第二栅极由以第二曝光时间图案化的第二光致抗蚀剂层限定，并且栅极长度的差异主要是由于第一和第二曝光时间。

39. 发明授权

US5723238A Inspection of lens error associated with lens heating in a photolithographic system 失效
标题翻译：在光刻系统中检查与透镜加热相关的透镜误差
公开(公告)号：US5723238A
公开(公告)日：1998-03-03
申请号：US760028
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F7/20 , G03C5/00
CPC分类号： G03F7/70058 , G03F7/70591 , G03F7/70891
摘要： A method of inspecting a lens includes projecting a first amount of radiation through a first test pattern and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.
摘要翻译：检查透镜的方法包括：通过第一测试图案和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，通过第二测试图案投射第二数量的辐射，并且透镜以提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据。以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。该方法非常适合于光刻系统，如步进和重复系统。

40. 发明授权

US06258646B1 CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 有权
标题翻译： CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法
公开(公告)号：US06258646B1
公开(公告)日：2001-07-10
申请号：US09149631
申请日：1998-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译：提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

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