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31. 发明授权

US07818692B2 Automated optimization of device structure during circuit design stage 有权
标题翻译：电路设计阶段器件结构自动化优化
公开(公告)号：US07818692B2
公开(公告)日：2010-10-19
申请号：US11946937
申请日：2007-11-29
申请人： Dureseti Chidambarrao , Jason Hibbeler , Richard Q. Williams
发明人： Dureseti Chidambarrao , Jason Hibbeler , Richard Q. Williams
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.
摘要翻译：提供了一种改进用于大规模集成电路的电路设计的方法，其表示在电路中互连的多个半导体器件。确定设计中的多个半导体器件中的一个的特征的边缘是否可以在第一方向上移动允许范围内的距离，使得提供电路的性能目标和匹配目标。如果是这样，边缘沿第一个方向移动计算的距离，以最佳地满足性能目标和匹配目标。对于多个半导体器件中的每一个可以重复上述步骤。如果需要，可以重复上述步骤，直到电路的性能目标和匹配目标被认为是充分的。

32. 发明授权

US07669170B2 Circuit layout methodology using via shape process 失效
标题翻译：使用通孔形状过程的电路布局方法
公开(公告)号：US07669170B2
公开(公告)日：2010-02-23
申请号：US11676185
申请日：2007-02-16
申请人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
发明人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

33. 发明申请

US20080104568A1 SYSTEMATIC YIELD IN SEMICONDUCTOR MANUFACTURE 失效
标题翻译：半导体制造中的系统性能
公开(公告)号：US20080104568A1
公开(公告)日：2008-05-01
申请号：US11966135
申请日：2007-12-28
申请人： Paul BERGERON , Jason Hibbeler , Gustavo Tellez
发明人： Paul BERGERON , Jason Hibbeler , Gustavo Tellez
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on a layer above the lower layer are formed on a more planar surface and thus are more likely to function properly. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，构建在下层上方的层上的结构形成在更平坦的表面上，因此更有可能正常地起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

34. 发明申请

US20070294648A1 IC Layout Optimization To Improve Yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US20070294648A1
公开(公告)日：2007-12-20
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

35. 发明申请

US20070240085A1 METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL 失效
标题翻译：使用关键区域分析工具计算VLSI设计对两个随机和系统缺陷的灵敏度的方法
公开(公告)号：US20070240085A1
公开(公告)日：2007-10-11
申请号：US11279300
申请日：2006-04-11
申请人： Jeanne Bickford , Jason Hibbeler , Juergen Koehl
发明人： Jeanne Bickford , Jason Hibbeler , Juergen Koehl
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081
摘要： A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
摘要翻译：估计集成电路产量的方法包括基于制造过程提供集成电路布局和一组系统缺陷。接下来，该方法通过修改集成电路布局中的结构以产生修改的结构来表示系统缺陷。更具体地，对于短路导致的缺陷，当结构包括较高的系统缺陷灵敏度水平时，该方法预先扩展结构，并且当结构包括较低的系统缺陷灵敏度水平时预结构。接下来，使用改进的结构对集成电路布局进行关键区域分析，其中使用点投掷，几何展开或Voronoi图。然后，该方法计算故障密度值，计算随机缺陷和系统缺陷。随后将故障密度值与预定值进行比较，其中使用来自目标制造过程的测试结构和/或屈服数据确定预定值。

36. 发明授权

US07188322B2 Circuit layout methodology using a shape processing application 失效
标题翻译：使用形状处理应用的电路布局方法
公开(公告)号：US07188322B2
公开(公告)日：2007-03-06
申请号：US10906591
申请日：2005-02-25
申请人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
发明人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

37. 发明申请

US20060195809A1 CIRCUIT LAYOUT METHODOLOGY 失效
标题翻译：电路布局方法
公开(公告)号：US20060195809A1
公开(公告)日：2006-08-31
申请号：US10906591
申请日：2005-02-25
申请人： John Cohn , Jason Hibbeler , Anthony Stamper , Jed Rankin
发明人： John Cohn , Jason Hibbeler , Anthony Stamper , Jed Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

38. 发明申请

US20110307846A1 METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
标题翻译：参数化分析与管理方法与系统
公开(公告)号：US20110307846A1
公开(公告)日：2011-12-15
申请号：US13216362
申请日：2011-08-24
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

39. 发明授权

US08042070B2 Methods and system for analysis and management of parametric yield 有权
标题翻译：参数收益分析与管理方法与系统
公开(公告)号：US08042070B2
公开(公告)日：2011-10-18
申请号：US11876853
申请日：2007-10-23
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

40. 发明申请

US20090106714A1 METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
标题翻译：参数化分析与管理方法与系统
公开(公告)号：US20090106714A1
公开(公告)日：2009-04-23
申请号：US11876853
申请日：2007-10-23
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F9/45
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

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