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31. 发明授权

US5761149A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US5761149A
公开(公告)日：1998-06-02
申请号：US679724
申请日：1996-07-12
申请人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
发明人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/105 , G11C8/00
CPC分类号： G11C29/80 , G11C11/418 , G11C29/83 , G11C8/14 , H01L27/105
摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.
摘要翻译：动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

32. 发明申请

US20080025346A1 Method and device for synchronizing and multiplexing asynchronous signals 审中-公开
标题翻译：用于同步和复用异步信号的方法和设备
公开(公告)号：US20080025346A1
公开(公告)日：2008-01-31
申请号：US11882002
申请日：2007-07-30
申请人： Tsugio Takahashi , Koichi Usami
发明人： Tsugio Takahashi , Koichi Usami
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , H04J3/0685 , H04J3/1611
摘要： A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.
摘要翻译：提出了一种用于同步和复用异步信号的方法和装置，其能够在不增加电路规模的情况下处理多个异步信号。时钟相位吸收部分允许相应的异步STM-N信号切换到系统时钟信号。根据系统时钟信号，MSOH终端部分，指针接收部分和存储部分在异步STM-N信号上串行执行MSOH终止处理，帧相位吸收处理等。在帧相位吸收之后产生的同步信号通过指针传输部分改变指针值等进行复用。

33. 发明授权

US5499202A Residue circuit 失效
标题翻译：残留电路
公开(公告)号：US5499202A
公开(公告)日：1996-03-12
申请号：US253057
申请日：1994-06-02
申请人： Tsugio Takahashi , Hitoshi Fujita , Hiroshi Okamoto
发明人： Tsugio Takahashi , Hitoshi Fujita , Hiroshi Okamoto
IPC分类号： G06F7/496 , G06F7/72 , G06F7/52 , G06F7/50
CPC分类号： G06F7/727
摘要： A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at a carry output, and a plurality of adders for summing bits having weight 2 to output weight 2 at a summing output and weight 1 at a carry output. With these adders, summing of respective bits of the dividend bits are performed taking the weights into account to repeat summing until the number of bits finally becomes 3 bits. Depending upon the pattern of this 3 bits, a remainder is output by a modulus 3 generation circuit.
摘要翻译：残余电路将除数的偶数位的权重设为1，并且将被除数的奇数位的权重作为2.该电路包括多个加法器，用于将加权1的位相加以在加法输出和权重2处输出权重1 以及多个加法器，用于对具有权重2的位进行求和，以在加法输出处输出权重2，并在进位输出处加权1。利用这些加法器，对于重复求和，考虑权重来执行除数比特的各个比特的相加，直到比特数最终变为3比特。根据该3位的模式，余数由模数3生成电路输出。

34. 发明授权

US5023648A Flash taking lens shutter camera 失效
标题翻译：闪光拍摄镜头快门摄像头
公开(公告)号：US5023648A
公开(公告)日：1991-06-11
申请号：US331304
申请日：1989-03-31
申请人： Hiroshi Meguro , Tsugio Takahashi , Hitoshi Aoki , Toru Kosaka
发明人： Hiroshi Meguro , Tsugio Takahashi , Hitoshi Aoki , Toru Kosaka
IPC分类号： G03B7/17 , G02B7/28 , G03B9/08 , G03B9/60 , G03B9/70 , G03B13/36 , G03B15/05
CPC分类号： G03B9/70 , G03B9/60
摘要： A lens shutter camera comprises a mode signal output device for outputting either a first flash mode signal or a second flash mode signal, a shutter driving device for effecting the opening movement of the lens shutter slowly and effecting the closing movement of the lens shutter quickly when the first flash mode signal is being outputted, and for effecting both of the opening and closing movements of the lens shutter slowly when the second flash mode signal is being outputted, and a flash start signal output device for outputting a flash start signal during the opening movement of the lens shutter when the first flash mode signal is being outputted, and for outputting the flash start signal during the closing movement of the lens shutter when the second flash mode signal is being outputted.
摘要翻译：镜头快门摄像机包括用于输出第一闪光模式信号或第二闪光模式信号的模式信号输出装置，用于缓慢地进行透镜快门的打开运动并快速实现透镜快门的关闭运动的快门驱动装置，正在输出第一闪光模式信号，并且用于当输出第二闪光模式信号时缓慢地实现透镜快门的打开和关闭运动;以及闪光启动信号输出装置，用于在打开期间输出闪光启动信号当输出第一闪光模式信号时透镜快门的移动，并且当输出第二闪光模式信号时在透镜快门的关闭运动期间输出闪光开始信号。

35. 发明授权

US09054675B2 Apparatuses and methods for adjusting a minimum forward path delay of a signal path 有权
标题翻译：用于调整信号路径的最小前进路径延迟的装置和方法
公开(公告)号：US09054675B2
公开(公告)日：2015-06-09
申请号：US13531341
申请日：2012-06-22
申请人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
发明人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.
摘要翻译：公开了与调整信号路径的最小前向路径延迟相关的装置和方法。一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大比所选延迟的最大计数值。

36. 发明授权

US07795941B2 Frame pulse signal latch circuit and phase adjustment method 有权
标题翻译：帧脉冲信号锁相电路及相位调整方式
公开(公告)号：US07795941B2
公开(公告)日：2010-09-14
申请号：US12391449
申请日：2009-02-24
申请人： Tsugio Takahashi
发明人： Tsugio Takahashi
IPC分类号： H03H11/26
CPC分类号： H03K5/05
摘要： A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK′; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit.
摘要翻译：帧脉冲信号锁存电路具有：脉冲宽度扩展单元，其输出具有比m时钟周期长的脉冲宽度的帧脉冲信号FPIN; 相位调整单元，其生成相位调整输出时钟CLK'; 锁存帧脉冲信号FPIN的触发器; 产生相对于帧脉冲信号FPOUT移位了1〜m个时钟的信号的赛车检测单元，并且基于帧脉冲信号FPOUT和时钟转换信号的“与”运算的结果来检测赛车状态 ; 以及控制单元，其顺序地选择并指示相位调整单元的不同相位调整量，基于检测到赛车状态的情况的最差相位调整量，确定最佳相位调整量，并且给出关于最优相位调整单元。

37. 发明授权

US06894547B2 Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit 有权
标题翻译：输出缓冲电路和具有这种输出缓冲电路的集成半导体电路器件
公开(公告)号：US06894547B2
公开(公告)日：2005-05-17
申请号：US10320059
申请日：2002-12-16
申请人： Tsugio Takahashi
发明人： Tsugio Takahashi
IPC分类号： G11C11/409 , G11C11/407 , H03K17/687 , H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/018585
摘要： An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.
摘要翻译：输出缓冲电路具有主驱动器，其包括用于驱动负载的第一pMOS晶体管和第一nMOS晶体管，以及用于与第一pMOS晶体管和第一nMOS晶体管共同驱动负载的第二pMOS晶体管和第二nMOS晶体管，以及包括用于驱动第一pMOS晶体管的第三pMOS晶体管和第三nMOS晶体管的预驱动器，用于驱动第一nMOS晶体管的第四pMOS晶体管和第四nMOS晶体管，用于驱动第一pMOS晶体管的第五nMOS晶体管与第三nMOS晶体管和用于与第四pMOS晶体管共同驱动第一nMOS晶体管的第五pMOS晶体管。

38. 发明授权

US6031779A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US6031779A
公开(公告)日：2000-02-29
申请号：US058147
申请日：1998-04-10
申请人： Yasushi Takahashi , Tsutomu Takahashi , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Shinji Bessho , Masayuki Hira
发明人： Yasushi Takahashi , Tsutomu Takahashi , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Shinji Bessho , Masayuki Hira
IPC分类号： G11C11/407 , G11C7/06 , G11C8/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/408 , G11C7/06 , G11C8/14 , G11C2207/065
摘要： Described herein is a dynamic memory. An N channel type voltage clamp MOSFET is provided which has a drain supplied with a supply voltage supplied from an external terminal, a gate to which a boosted constant voltage is applied, and a source which outputs a constant voltage. The clamp voltage outputted from the source of the voltage clamp MOSFET is supplied to a common source line for each of P channel type amplification MOSFETs constituting a sense amplifier via a P channel type first power MOSFET switch-controlled by a sense amplifier activation signal, as a voltage for operating the sense amplifier. Further, the constant voltage outputted from the source of the voltage clamp MOSFET is supplied to an N-well region in which the P channel type first power MOSFET and the P channel type MOSFETs constituting the sense amplifier are formed, as a bias voltage.
摘要翻译：这里描述的是动态存储器。提供了一种N沟道型电压钳位MOSFET，其具有供给从外部端子提供的电源电压的漏极，施加升压恒定电压的栅极和输出恒定电压的源极。从电压钳位MOSFET的源极输出的钳位电压通过由读出放大器激活信号开关控制的P沟道型第一功率MOSFET构成读出放大器的每个P沟道型放大器MOSFET，被提供给公共源极线，如用于操作读出放大器的电压。此外，从电压钳位MOSFET的源极输出的恒定电压被提供给形成P沟道型第一功率MOSFET和构成读出放大器的P沟道型MOSFET的N阱区域作为偏置电压。

39. 发明授权

US5831910A Semiconductor integrated circuit utilizing overdriven differential amplifiers 失效
标题翻译：采用过驱动差分放大器的半导体集成电路
公开(公告)号：US5831910A
公开(公告)日：1998-11-03
申请号：US689989
申请日：1996-08-16
申请人： Yukihide Suzuki , Noriaki Kubota , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
发明人： Yukihide Suzuki , Noriaki Kubota , Kouji Arai , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065 , G11C7/06
摘要： A semiconductor integrated circuit is provided in which a differential amplifier circuit such as a sense amplifier is operated at high speed even if the operating voltage is reduced. To achieve this, a MOS transistor for supplying the operating voltage to a drive line on the high-potential side of a differential amplifier circuit is of N-channel type and the amplitude of a switching control signal for controlling this transistor is the potential of the step-up voltage produced by stepping up a supply voltage in level. The output voltage of an internal step-up circuit for achieving a word-line selection level is utilizable as the step-up voltage.
摘要翻译：提供了一种半导体集成电路，其中诸如读出放大器的差分放大器电路即使在工作电压降低的情况下也以高速运行。为了实现这一点，用于向差分放大器电路的高电位侧的驱动线提供工作电压的MOS晶体管是N沟道型，并且用于控制该晶体管的开关控制信号的幅度是通过提高电源电压而产生的升压电压。用于实现字线选择电平的内部升压电路的输出电压可用作升压电压。

40. 发明授权

US5764580A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5764580A
公开(公告)日：1998-06-09
申请号：US689921
申请日：1996-08-16
申请人： Yukihide Suzuki , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
发明人： Yukihide Suzuki , Tsugio Takahashi , Shunichi Sukegawa , Koichi Abe
IPC分类号： G11C7/06 , G11C7/22 , G11C7/00
CPC分类号： G11C7/065 , G11C7/22
摘要： A semiconductor integrated circuit capable of preventing the excessive overdriving of sense amplifiers when the supply voltage fed thereto is raised. The integrated circuit has differential amplifiers for amplifying a potential difference on complementary signal lines, and a control circuit for generating a first driving control signal for supplying the differential amplifiers with a first driving voltage as an overdriving power supply therefor. The control circuit further generates a second driving control signal for supplying the differential amplifiers with a second driving voltage which is activated after the activated first driving control signal is deactivated and which is lower in level than the first driving voltage. The control circuit includes a MOS circuit as a delay circuit composed of MOS transistors for defining a time interval from the time the first driving control signal is activated until the second driving control signal is activated. With this arrangement, the period during which the overdriving voltage is applied is variable in dependence on the level of the supply voltage such that the overdrive period is relatively short if the supply voltage is high and relatively long if the supply voltage is low.
摘要翻译：一种半导体集成电路，其能够在提供供给电压时防止读出放大器的过度驱动。集成电路具有用于放大互补信号线上的电位差的差分放大器，以及用于产生第一驱动控制信号的控制电路，用于向差分放大器提供第一驱动电压作为过驱动电源。控制电路还产生第二驱动控制信号，用于向差分放大器提供第二驱动电压，该第二驱动电压在激活的第一驱动控制信号被去激活之后被激活，并且其电位低于第一驱动电压。控制电路包括作为由MOS晶体管组成的延迟电路的MOS电路，用于定义从第一驱动控制信号激活直到第二驱动控制信号被激活的时间间隔。通过这种布置，施加过驱动电压的周期可以根据电源电压的电平而变化，使得如果电源电压较高并且如果电源电压低，则过驱动周期相对较短。

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