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    • 35. 发明授权
      US08674775B2 Out-of-plane resonator 有权
    • Out-of-plane resonator
    • 平面外谐振器
    • US08674775B2
    • 2014-03-18
    • US13173449
    • 2011-06-30
    • Mehrnaz Motiee , Emmanuel P. Quevy , David H. Bernstein
    • Mehrnaz Motiee , Emmanuel P. Quevy , David H. Bernstein
    • H03B5/30
    • H03H9/2457 , H03H9/2452 , H03H2009/02299 , H03H2009/02511
    • A microelectromechanical system (MEMS) device includes a resonator anchored to a substrate. The resonator includes a first strain gradient statically deflecting a released portion of the resonator in an out-of-plane direction with respect to the substrate. The resonator includes a first electrode anchored to the substrate. The first electrode includes a second strain gradient of a released portion of the first electrode. The first electrode is configured to electrostatically drive the resonator in a first mode that varies a relative amount of displacement between the resonator and the first electrode. The resonator may include a resonator anchor anchored to the substrate. The first electrode may include an electrode anchor anchored to the substrate in close proximity to the resonator anchor. The electrode anchor may be positioned relative to the resonator anchor to substantially decouple dynamic displacements of the resonator relative to the electrode from changes to the substrate.
    • 微机电系统（MEMS）装置包括锚定到基板的谐振器。 谐振器包括使第一应变梯度在相对于衬底的平面外方向上静态偏转谐振器的释放部分。 谐振器包括锚定到基板的第一电极。 第一电极包括第一电极的释放部分的第二应变梯度。 第一电极被配置为以改变谐振器和第一电极之间的相对的位移量的第一模式静电驱动谐振器。 谐振器可以包括锚定到衬底的谐振器锚。 第一电极可以包括锚固到靠近谐振器锚的衬底的电极锚。 电极锚定件可以相对于谐振器锚固件定位，以基本上使谐振器相对于电极的动态位移与基板的变化相分离。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 39. 再颁专利
      USRE30331E Data processing system having a unique CPU and memory timing relationship and data path configuration 失效
    • Data processing system having a unique CPU and memory timing relationship and data path configuration
    • 数据处理系统具有独特的CPU和存储器时序关系以及数据路径配置
    • USRE30331E
    • 1980-07-08
    • US19578
    • 1979-03-12
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F9/312 , G06F9/40 , G06F13/42
    • G06F9/30043 , G06F1/04 , G06F13/4243 , G06F9/226 , G06F9/4425
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 40. 发明授权
      US4075692A Data path configuration for a data processing system 失效
    • Data path configuration for a data processing system
    • 数据处理系统的数据路径配置
    • US4075692A
    • 1978-02-21
    • US737416
    • 1976-11-01
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F13/18 , G06F13/42 , G06F7/38
    • G06F1/04 , G06F13/18 , G06F13/4243 , G06F9/226
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.
    • 一种数据处理系统，其中中央处理器单元与一个或多个存储器单元异步操作，独立于存储器单元的操作速度，其中中央处理器定时信号和存储器定时信号具有预定的相位关系。 中央处理器单元被布置成即使当存储器单元被使能时仍然保持操作，除非在预选条件下由存储器单元的信号禁用该处理器单元。 中央处理器产生多个操作指令信号以传送到存储器单元，以允许后者通过启用存储器单元来执行其期望的功能，从而阻止数据从存储器单元传送到数据总线并且允许数据从 中央处理器单元，当数据可接受这样的存储。 在中央处理器单元处产生进一步的操作指令信号，以便允许从存储器单元读取的数据在中央处理器单元处被修改，并且在这样的修改之后被存储在存储器单元中。 在存储器单元内部产生另外的操作指令信号，以防止存储器单元中的其中一个存储器件中的其中一个处于操作中时所有其他存储器件的操作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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