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31. 发明授权

US07574680B1 Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权
标题翻译：专用于可编程存储器架构和芯片上互连网络的方法和装置
公开(公告)号：US07574680B1
公开(公告)日：2009-08-11
申请号：US11699097
申请日：2007-01-29
申请人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
发明人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，接收包括存储器系统的属性的规范数据。响应于规范数据生成存储器系统的逻辑描述。逻辑描述定义了存储器组件和存储器互连组件。响应于逻辑描述生成存储器系统的物理描述。物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。存储器电路包括由存储器互连部件定义的互连拓扑。

32. 发明授权

US07328335B1 Bootable programmable logic device for internal decoding of encoded configuration data 有权
标题翻译：可引导可编程逻辑器件，用于编码配置数据的内部解码
公开(公告)号：US07328335B1
公开(公告)日：2008-02-05
申请号：US10956989
申请日：2004-10-01
申请人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
发明人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F9/24
CPC分类号： H03K19/17748 , G06F15/7867 , H03K19/17732 , H03K19/17768
摘要： Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.
摘要翻译：描述用于解码配置数据的方法和装置。具有配置接口的可编程逻辑器件耦合到在配置接口耦合的引导存储器。引导内存包含用于通过配置界面配置可编程逻辑器件的引导内核。引导核心包括配置解码器核心和内部处理器接口核心。引导核心可以进一步包括处理器核心。配置解码器核心提供可编程逻辑器件内部的外围接口，并且引导存储器包含用于解码编码数据的至少一组指令和用于将解码的编码数据写入可编程逻辑器件的配置存储器的至少一个存储库。编码数据经由外围接口从数据存储器获得。

33. 发明授权

US07228520B1 Method and apparatus for a programmable interface of a soft platform on a programmable logic device 有权
标题翻译：用于可编程逻辑器件上的软平台的可编程接口的方法和装置
公开(公告)号：US07228520B1
公开(公告)日：2007-06-05
申请号：US10769331
申请日：2004-01-30
申请人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
发明人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，为集成电路内的多个线程定义第一属性。为与集成电路相关联的存储器定义第二属性。为与存储器和多个线程中的至少一个相关联的互连拓扑定义第三属性。为与至少一个存储器和多个线程的接口定义第四属性。

34. 发明授权

US07131077B1 Using an embedded processor to implement a finite state machine 有权
标题翻译：使用嵌入式处理器实现有限状态机
公开(公告)号：US07131077B1
公开(公告)日：2006-10-31
申请号：US10402659
申请日：2003-03-28
申请人： Philip B. James-Roxby , Eric R. Keller
发明人： Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and System for implementing a Finite State Machine (FSM) using software executed on a processor and having accurate timing information is described, where the accurate timing information is determined without the need to execute the software. An exemplary embodiment includes an IC having an embedded processor and a programmable logic fabric, where part or all of an FSM is implemented using assembly language code stored in a memory, for example, a cache memory, of the embedded processor.
摘要翻译：描述了使用在处理器上执行并具有准确定时信息的软件实现有限状态机（FSM）的方法和系统，其中确定准确的定时信息而不需要执行软件。示例性实施例包括具有嵌入式处理器和可编程逻辑结构的IC，其中使用存储在嵌入式处理器的存储器（例如，高速缓冲存储器）中的汇编语言代码来实现FSM的部分或全部。

35. 发明授权

US07076596B1 Method of and apparatus for enabling a hardware module to interact with a data structure 有权
标题翻译：用于使得硬件模块能够与数据结构交互的方法和装置
公开(公告)号：US07076596B1
公开(公告)日：2006-07-11
申请号：US10354493
申请日：2003-01-30
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F12/00
CPC分类号： G06F12/0223
摘要： A method of enabling a hardware module to interact with a data structure is disclosed. The method comprises the steps of enabling the hardware module to determine an address of a data item referenced by the data structure; providing a base address for the data structure to the hardware module; and accessing a data item referenced by the data structure. A field programmable gate array having a hardware module capable of interacting with a data structure is also described. The field programmable gate array comprises a memory having a data structure; a hardware module coupled to the memory and comprising a lookup table; and a target address generated by the hardware module for a data item of the data structure.
摘要翻译：公开了一种使得硬件模块能够与数据结构交互的方法。该方法包括以下步骤：使得硬件模块能够确定由数据结构引用的数据项的地址; 为硬件模块提供数据结构的基址; 并访问由数据结构引用的数据项。还描述了具有能够与数据结构交互的硬件模块的现场可编程门阵列。现场可编程门阵列包括具有数据结构的存储器; 耦合到所述存储器并且包括查找表的硬件模块; 以及由硬件模块为数据结构的数据项产生的目标地址。

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