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31. 发明申请

US20090167770A1 BOOSTING GRAPHICS PERFORMANCE BASED ON EXECUTING WORKLOAD 有权
标题翻译：基于执行工作负载提升图形性能
公开(公告)号：US20090167770A1
公开(公告)日：2009-07-02
申请号：US11967207
申请日：2007-12-30
申请人： ADITYA NAVALE , Eric C. Samson
发明人： ADITYA NAVALE , Eric C. Samson
IPC分类号： G06T1/20
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.
摘要翻译：公开了一种包括工作负载检测软件的新型图形系统。根据硬件执行的操作，新颖的图形系统可提高集成显卡芯片组中的图形硬件的电压和频率，以获得性能优势或省电优势。

32. 发明申请

US20150241954A1 Apparatus and Method for Determining the Number of Execution Units to Keep Active in a Processor 审中-公开
标题翻译：用于确定在处理器中保持活动的执行单元数量的装置和方法
公开(公告)号：US20150241954A1
公开(公告)日：2015-08-27
申请号：US14697553
申请日：2015-04-27
申请人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.
摘要翻译：描述了在处理器核心中包括多个执行单元的处理器。处理器还可以包括功率管理电路，以从多个配置中确定具有最低功率成本的配置，每个配置对于相同的主动性能状态具有不同数量的启用的执行单元。一种方法可以包括：通过处理器的功率管理电路确定来自多个配置的具有最低功率成本的配置，每个配置在处理器的处理器核心中具有不同数量的启用的执行单元，用于相同的主动性能状态。

33. 发明申请

US20150170317A1 Load Balancing for Consumer-Producer and Concurrent Workloads 审中-公开
标题翻译：消费者生产者和并发工作负载的负载平衡
公开(公告)号：US20150170317A1
公开(公告)日：2015-06-18
申请号：US14132028
申请日：2013-12-18
申请人： Eric C. Samson , Murali Ramadoss
发明人： Eric C. Samson , Murali Ramadoss
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/5083 , G06F9/5094 , Y02D10/22
摘要： In accordance with some embodiments, a system may detect whether or not a workload currently being worked on by two processors is serialized or concurrent. A workload is serialized or a producer consumer workload when the workload is such that one processor must receive the output from the other processor before it can begin. A workload is concurrent if both processors can work on the workload at the same time. In one embodiment, the nature of memory accesses can be used to determine the workload type. For example, when both processors use a shared virtual memory, the memory accesses can be tracked to detect whether serialized or concurrent workloads are involved.
摘要翻译：根据一些实施例，系统可以检测两个处理器当前正在工作的工作负载是否被序列化或并发。当工作负载使得一个处理器必须在其开始之前从另一个处理器接收输出时，工作负载被序列化或生产者消费者工作负载。如果两个处理器可以同时处理工作负载，则工作负载是并发的。在一个实施例中，存储器访问的性质可以用于确定工作负载类型。例如，当两个处理器使用共享虚拟内存时，可以跟踪内存访问以检测是否涉及序列化或并发工作负载。

34. 发明申请

US20150170315A1 Controlling Frame Display Rate 审中-公开
标题翻译：控制帧显示速率
公开(公告)号：US20150170315A1
公开(公告)日：2015-06-18
申请号：US14108442
申请日：2013-12-17
申请人： Eric C. Samson , Barnes Cooper
发明人： Eric C. Samson , Barnes Cooper
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A system on a chip may include a central processing unit and a graphics processing unit. Based on a user specified target frame rate, it is determined whether a previous processor frame duration for either both of said central and graphics processing unit is too long. It so, at least one of the processors' idle times is decreased. In some embodiments, the frame rate is accessed only if the system on a chip is power limited. In some embodiments, the start of work on the graphics processing unit may be locked to a benchmark such as a v-sync signal or a completion of work on the graphics processor.
摘要翻译：芯片上的系统可以包括中央处理单元和图形处理单元。基于用户指定的目标帧速率，确定所述中央处理单元和图形处理单元两者的先前处理器帧持续时间是否过长。因此，至少有一个处理器的空闲时间减少。在一些实施例中，仅当芯片上的系统被功率限制时才访问帧速率。在一些实施例中，图形处理单元上的开始工作可以被锁定到诸如v同步信号或图形处理器上的完成工作之类的基准。

35. 发明授权

US09037889B2 Apparatus and method for determining the number of execution cores to keep active in a processor 有权
标题翻译：用于确定在处理器中保持活动的执行核心数量的装置和方法
公开(公告)号：US09037889B2
公开(公告)日：2015-05-19
申请号：US13631679
申请日：2012-09-28
申请人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
发明人： Avinash N. Ananthakrishnan , Julien Fefe Sebot , Jay D. Schwartz , Stephen H. Gunther , Eric C. Samson
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译：描述了包括多个执行核心的处理器。处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使处理器在基本上线性的功率消耗与频率操作区域中工作，使得作为功率消耗的功能的性能增益与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。

36. 发明授权

US08781641B2 Method and apparatus for external processor thermal control 有权
标题翻译：外部处理器热控制的方法和装置
公开(公告)号：US08781641B2
公开(公告)日：2014-07-15
申请号：US12980648
申请日：2010-12-29
申请人： Eric C. Samson , John William Horigan , Robert T. Jackson , Ticky Thakkar
发明人： Eric C. Samson , John William Horigan , Robert T. Jackson , Ticky Thakkar
IPC分类号： G05D23/00
CPC分类号： G06F1/206
摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy.
摘要翻译：公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。从组件可以发送第二信号以指示从组件的温度已超过其温度。然后，主组件将启动主组件的节流以降低计算系统的整体温度。主部件可以被节流到比从属部件小的程度。可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。

37. 发明申请

US20130111236A1 Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor 有权
公开(公告)号：US20130111236A1
公开(公告)日：2013-05-02
申请号：US13282947
申请日：2011-10-27
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessman , Ryan Wells
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

38. 发明申请

US20130054992A1 DYNAMIC CONTROL OF REDUCED VOLTAGE STATE OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER 有权
公开(公告)号：US20130054992A1
公开(公告)日：2013-02-28
申请号：US13629046
申请日：2012-09-27
申请人： Eric C. Samson , Aditya Navale
发明人： Eric C. Samson , Aditya Navale
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3218 , G06F1/3237 , G06F1/324 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

39. 发明授权

US08243085B2 Boosting graphics performance based on executing workload 有权
标题翻译：基于执行工作负载提升图形性能
公开(公告)号：US08243085B2
公开(公告)日：2012-08-14
申请号：US11967207
申请日：2007-12-30
申请人： Aditya Navale , Eric C. Samson
发明人： Aditya Navale , Eric C. Samson
IPC分类号： G06F13/14
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.
摘要翻译：公开了一种包括工作负载检测软件的新型图形系统。根据硬件执行的操作，新颖的图形系统可提高集成显卡芯片组中的图形硬件的电压和频率，以获得性能优势或省电优势。

40. 发明申请

US20120095607A1 Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems 审中-公开
标题翻译：通过动态管理存储器和输入/输出子系统的能量效率和节能的方法，装置和系统
公开(公告)号：US20120095607A1
公开(公告)日：2012-04-19
申请号：US13335638
申请日：2011-12-22
申请人： Ryan D. Wells , Avinash N. Ananthakrishnan , Inder Sodhi , Eric C. Samson , Joydeep Ray
发明人： Ryan D. Wells , Avinash N. Ananthakrishnan , Inder Sodhi , Eric C. Samson , Joydeep Ray
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.
摘要翻译：根据本发明的一个实施例，集成电路设备包括互连，至少一个计算引擎和控制单元。所述控制单元经由所述互连耦合到所述至少一个计算引擎，以分析来自所述至少一个计算引擎的启发式信息，并且基于所述启发式信息来增加或减少所述互连的带宽。

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