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31. 发明授权

US5101125A Semiconductor integrated circuit with improved I/O structure with ECL to CMOS to ECL conversion 失效
标题翻译：具有改进的I / O结构的半导体集成电路，具有ECL到CMOS到ECL转换
公开(公告)号：US5101125A
公开(公告)日：1992-03-31
申请号：US511747
申请日：1990-04-20
申请人： Hiroyuki Hara , Yasuhiro Sugimoto
发明人： Hiroyuki Hara , Yasuhiro Sugimoto
IPC分类号： H01L27/082 , H01L21/8222 , H03K19/0175
CPC分类号： H03K19/017518
摘要： A semiconductor integrated circuit includes a bias voltage generating circuit and first- and second-level signal generating circuits. The bias voltage generating circuit includes a bandgap reference circuit for generating a first fixed voltage as a first bias voltage and a second fixed voltage. A second bias voltage is generated on the basis of the second fixed voltage. The second-level signal generating circuit receives a predetermined first-level signal and generates a predetermined second-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit. The first-level signal generating circuit receives the predetermined second-level signal and generates the predetermined first-level signal on the basis of the first and second bias voltages generated by the bias voltage generating circuit.

32. 发明授权

US4831579A Full adder circuit having an exclusive-OR circuit 失效
标题翻译：全加法电路具有异或电路
公开(公告)号：US4831579A
公开(公告)日：1989-05-16
申请号：US734142
申请日：1985-05-15
申请人： Hiroyuki Hara , Yasuhiro Sugimoto
发明人： Hiroyuki Hara , Yasuhiro Sugimoto
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , G06F7/523 , G06F7/53 , H03K19/21
CPC分类号： G06F7/501 , G06F2207/4806
摘要： A logic operation circuit includes an exclusive-OR circuit for receiving first and second logic sum signals of preceeding stages, a sum signal selection circuit for selectively generating a carry output signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating the carry input signal or the first logic sum signal as a sum signal in accordance with the output signal from the exclusive-OR circuit. The exclusive-OR circuit includes a double balance type differential amplifier connected between first and second power source terminals, and the sum signal selection circuit includes a double balance differential amplifier operated in accordance with the output signal from the exclusive-OR circuit and the carry input signal and connected between the first and second power source terminals.
摘要翻译：逻辑运算电路包括用于接收前级的第一和第二逻辑和信号的异或电路，和信号选择电路，用于根据输出信号选择性地产生进位输出信号或其反相信号作为进位输出信号来自异或电路，以及进位输出信号选择电路，用于根据来自异或电路的输出信号选择性地产生进位输入信号或第一逻辑和信号作为和信号。异或电路包括连接在第一和第二电源端子之间的双平衡型差分放大器，并且和信号选择电路包括根据来自异或电路的输出信号和进位输入端操作的双平衡差分放大器信号并连接在第一和第二电源端子之间。

33. 发明授权

US4725982A Tri-state buffer circuit 失效
标题翻译：三态缓冲电路
公开(公告)号：US4725982A
公开(公告)日：1988-02-16
申请号：US845540
申请日：1986-03-28
申请人： Hiroyuki Hara , Yasuhiro Sugimoto
发明人： Hiroyuki Hara , Yasuhiro Sugimoto
IPC分类号： H03K19/0175 , H01L21/8249 , H01L27/06 , H03K19/082 , H03K19/094 , H03K19/0944 , H03K19/0952 , G11C11/34 , G11C7/00 , G11C11/56 , H01L27/02
CPC分类号： H03K19/09425 , H03K19/0826 , H03K19/09448
摘要： A tri-state buffer circuit according to the present invention comprises a switching circuit connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have a first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal; an inverter circuit connected to said switching circuit, and the first power supply terminal for inverting the first switching signal (A) from said switching circuit as an output signal; a selection circuit connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; a first type bipolar transistor whose base is connected to said inverter circuit, whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and a first type bipolar transister whose base is connected to said selection circuit, whose collecter is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.
摘要翻译：根据本发明的三态缓冲电路包括连接到输入端（IN），三态和反相三态输入端（T，＆amp; T和T）的开关电路和用于产生第一和仅在三态信号处于第一电平时分别具有第一和第二电平的第二开关信号（A，B），而与输入信号的电平无关; 连接到所述开关电路的逆变器电路和用于将来自所述开关电路的所述第一开关信号（A）反相作为输出信号的所述第一电源端子; 连接到所述开关电路和逆变器电路的选择电路，用于仅在三态信号处于第一电平时保持具有等于反相信号的第二电平的信号; 第一型双极晶体管，其基极连接到所述逆变器电路，其集电器连接到第一电源端子，并且其发射极连接到三态电路的输出端子; 以及第一型双极转移器，其基极连接到所述选择电路，其集电器连接到三态电路的输出端，并且其发射极连接到第二电源端子。

34. 发明授权

US09202149B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US09202149B2
公开(公告)日：2015-12-01
申请号：US14076218
申请日：2013-11-10
申请人： Hiroyuki Hara
发明人： Hiroyuki Hara
IPC分类号： G06F3/12 , G06K15/02 , G06K15/00
CPC分类号： G06K15/181 , G06F3/1297 , G06K15/00 , G06K15/02 , G06K15/1827 , G06K15/1851 , G06K15/1857 , G06K15/1863 , H04N2201/0082
摘要： A CPU performs the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) in the order of (a), (b) (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).
摘要翻译： CPU执行以下步骤：（a）使压缩/解压缩处理器解压缩除频带中的第一块以外的数据区域中的三个频带之一的压缩数据，并将解压缩的位图数据存储在数据区域中; （b）对频带中的每个中间数据块进行光栅化，并合成光栅化数据和频带中的解压缩位图数据; 并且使压缩/解压缩处理器压缩合成位图数据并将压缩数据存储在数据区中。 CPU在不同的各个任务中并行执行步骤（a）至（c），并且按照（a），（b）（c）的顺序对每个中间代码执行步骤（a）至（c）在步骤（a）至（c）中的每一个依次使用第1至第3位图数据区域的每个频带中的块。

35. 发明授权

US08736889B2 Image forming apparatus that buffers data in a storage device and reduces delays in process 有权
标题翻译：图像形成装置，用于缓冲存储装置中的数据并减少处理中的延迟
公开(公告)号：US08736889B2
公开(公告)日：2014-05-27
申请号：US13434440
申请日：2012-03-29
申请人： Hiroyuki Hara
发明人： Hiroyuki Hara
IPC分类号： G06K15/00
CPC分类号： H04N1/0083 , G06K15/1851 , H04N1/21
摘要： An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.
摘要翻译：图像形成装置包括处理器和将频带数据写入存储装置并读取频带数据的存储控制器。处理器：（a）产生一个写入的进程和一个读取的进程; （b）通过写入侧进程生成写入线程; （c）通过读取侧处理生成读取侧线程和文件读取线程; （d）向存储装置内的识别符通知读取侧处理，使存储控制器依次写入频带数据; 和（e）请求文件读取线程使存储控制器顺序地读取对应于该标识符的频带数据，并使存储控制器顺序读出频带数据和一个或多个后续频带数据。

36. 发明授权

US08604725B2 Semiconductor device and drive method of electrostatic actuator 失效
标题翻译：静电执行器的半导体器件和驱动方法
公开(公告)号：US08604725B2
公开(公告)日：2013-12-10
申请号：US13719924
申请日：2012-12-19
申请人： Tamio Ikehashi , Takayuki Miyazaki , Hiroyuki Hara
发明人： Tamio Ikehashi , Takayuki Miyazaki , Hiroyuki Hara
IPC分类号： H01L41/04
CPC分类号： H02N1/006
摘要： According to one embodiment, a semiconductor device includes an electrostatic actuator including first and second lower electrodes, an upper electrode, and an insulating film provided between the upper electrode and the first and second lower electrodes, the first lower electrode and upper electrode configuring a first variable capacitance element, the second lower electrode and upper electrode configuring a second variable capacitance element, a first fixed capacitance element connected to the first lower electrode, a second fixed capacitance element connected to the second lower electrode, and a detection circuit connected to the upper electrode and configured to detect a charge amount stored in the insulating film.
摘要翻译：根据一个实施例，半导体器件包括静电致动器，其包括第一和第二下部电极，上部电极和设置在上部电极与第一和第二下部电极之间的绝缘膜，第一下部电极和上部电极构成第一可变电容元件，第二下电极和构成第二可变电容元件的上电极，连接到第一下电极的第一固定电容元件，连接到第二下电极的第二固定电容元件，以及连接到上电极的检测电路电极，并且被配置为检测存储在绝缘膜中的电荷量。

37. 发明授权

US08415982B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US08415982B2
公开(公告)日：2013-04-09
申请号：US13178694
申请日：2011-07-08
申请人： Chenkong Teh , Hiroyuki Hara
发明人： Chenkong Teh , Hiroyuki Hara
IPC分类号： H03K19/096 , H03K19/094 , H03K19/20 , H03K3/00 , H03K5/12 , H03B1/00
CPC分类号： H03K3/356191
摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.
摘要翻译：一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。半导体集成电路器件以小的面积确保足够的延迟时间。

38. 发明授权

US07999575B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07999575B2
公开(公告)日：2011-08-16
申请号：US12701730
申请日：2010-02-08
申请人： Chenkong Teh , Hiroyuki Hara
发明人： Chenkong Teh , Hiroyuki Hara
IPC分类号： H03K19/20 , H03K19/096 , H03K3/356
CPC分类号： H03K3/356191
摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.
摘要翻译：一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。半导体集成电路装置以小的面积确保足够的延迟时间。

39. 发明申请

US20110039975A1 ANTIFOULING COMPOSITION, PROCESS FOR ITS PRODUCTION AND ARTICLE TREATED THEREWITH 有权
标题翻译：抗生素组合物及其生产工艺及其处理方法
公开(公告)号：US20110039975A1
公开(公告)日：2011-02-17
申请号：US12913900
申请日：2010-10-28
申请人： Hiroyuki Hara , Shuichiro Sugimoto , Takao Hirono
发明人： Hiroyuki Hara , Shuichiro Sugimoto , Takao Hirono
IPC分类号： C09D5/16
CPC分类号： D06M15/277 , C08F214/06 , C08F220/22 , C08F220/58 , C08F222/14 , C08F2220/1891
摘要： To provide a process for efficiently producing a fluorine type antifouling composition employing a short chain Rf group, which can be made in the form of an aqueous dispersion containing substantially no volatile organic solvent and has a good soil release property (SR property).A process for producing an antifouling composition, which comprises a step of subjecting monomer components (Z) comprising from 30 to 80 mass % of a monomer (a) having a polyfluoroalkyl group in which the number of carbon atoms to which fluorine atoms are bonded is from 4 to 6, and from 20 to 70 mass % of a monomer (b) having no polyfluoroalkyl group and having a hydrophilic group, to solution polymerization in a volatile organic solvent having a boiling point of at most 100° C. in the presence of a surfactant (c) comprising an ethylene oxide adduct of 2,4,7,9-tetramethyl-5-decyne-4,7-diol to form a fluorocopolymer (A), and a step of volatilizing the volatile organic solvent after the solution polymerization and adding an aqueous medium to form an aqueous dispersion.
摘要翻译：为了提供一种能够有效地制造使用短链Rf基的氟型防污组合物的方法，其可以基本上不含挥发性有机溶剂的水性分散体的形式制备并且具有良好的去污性能（SR性能）。一种防污组合物的制造方法，其特征在于，包括含有30〜80质量％的具有与氟原子键合的碳原子数的多氟烷基的单体（a）的单体成分（Z）的工序是 4〜6质量％，20〜70质量％的不具有多氟烷基且具有亲水性基团的单体（b）在沸点为100℃以下的挥发性有机溶剂中进行溶液聚合，包含2,4,7,9-四甲基-5-癸炔-4,7-二醇的环氧乙烷加合物以形成含氟共聚物（A）的表面活性剂（c），以及在溶液之后使挥发性有机溶剂挥发的步骤聚合并加入水性介质以形成水分散体。

40. 发明授权

US07781964B2 Organic electroluminescent device and electronic apparatus 有权
标题翻译：有机电致发光器件和电子设备
公开(公告)号：US07781964B2
公开(公告)日：2010-08-24
申请号：US11684944
申请日：2007-03-12
申请人： Hiroyuki Hara , Sumio Utsunomiya , Daisuke Abe , Masayoshi Todorokihara , Kazuyuki Miyashita
发明人： Hiroyuki Hara , Sumio Utsunomiya , Daisuke Abe , Masayoshi Todorokihara , Kazuyuki Miyashita
IPC分类号： H01J1/62
CPC分类号： H01L27/3244 , H01L27/3265 , H01L27/3276
摘要： An organic electroluminescent device includes a substrate that is conductive at least on a first surface; a first insulating film located on the first surface of the substrate and including a portion of a first opening, a portion of a second opening, and a portion of a third opening; a semiconductor film located on the first insulating film and receiving a current from the first surface of the substrate via the portion of a first opening; a second insulating film located on the semiconductor film and in contact with the substrate via the portion of a second opening; a capacitance electrode located on the second insulating film; a gate electrode located on the second insulating film and overlapping the semiconductor film; an intermediate insulating film located on the gate electrode and capacitance electrode; a pixel electrode located on the intermediate insulating film and receiving a current via the semiconductor film; a light-emitting layer located on the pixel electrode; a common electrode located on the light-emitting layer; and a power supply section located on the first insulating film and supplying a current to the first surface of the substrate via the portion of a third opening. The second insulating film is interposed between the capacitance electrode and the substrate via the portion of a second opening.
摘要翻译：有机电致发光器件包括至少在第一表面上导电的衬底; 第一绝缘膜，位于基板的第一表面上，并且包括第一开口的一部分，第二开口的一部分和第三开口的一部分; 半导体膜，位于所述第一绝缘膜上，并且经由所述第一开口的所述部分从所述基板的所述第一表面接收电流; 位于所述半导体膜上并经由所述第二开口部分与所述基板接触的第二绝缘膜; 位于所述第二绝缘膜上的电容电极; 位于所述第二绝缘膜上且与所述半导体膜重叠的栅电极; 位于栅电极和电容电极上的中间绝缘膜; 位于中间绝缘膜上并经由半导体膜接收电流的像素电极; 位于像素电极上的发光层; 位于发光层上的公共电极; 以及电源部，其位于所述第一绝缘膜上，并且经由所述第三开口的所述部分向所述基板的所述第一表面供给电流。第二绝缘膜通过第二开口的一部分介于电容电极和基板之间。

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