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31. 发明授权

US06898135B2 Latch type sense amplifier method and apparatus 失效
标题翻译：锁存型读出放大器的方法和装置
公开(公告)号：US06898135B2
公开(公告)日：2005-05-24
申请号：US10606587
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/065 , G11C7/1051
摘要： Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.
摘要翻译：公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。

32. 发明申请

US20090116307A1 LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE 有权
标题翻译：提高字线电压和存储单元性能的级别更换
公开(公告)号：US20090116307A1
公开(公告)日：2009-05-07
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

33. 发明授权

US07444525B2 Methods and apparatus for reducing leakage current in a disabled SOI circuit 有权
标题翻译：用于减少残留SOI电路中漏电流的方法和装置
公开(公告)号：US07444525B2
公开(公告)日：2008-10-28
申请号：US11137234
申请日：2005-05-25
申请人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
发明人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/0016
摘要： Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
摘要翻译：方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

34. 发明授权

US07170316B2 Programmable logic array latch 失效
标题翻译：可编程逻辑阵列锁存器
公开(公告)号：US07170316B2
公开(公告)日：2007-01-30
申请号：US10982018
申请日：2004-11-05
申请人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译：公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。第二逻辑阵列耦合到第一逻辑阵列。输出锁存器耦合到第二逻辑阵列。

35. 发明授权

US06885596B2 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM 失效
标题翻译：使用SRAM中的移位寄存器进行字线/位线冗余控制的装置和方法
公开(公告)号：US06885596B2
公开(公告)日：2005-04-26
申请号：US10606584
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/806
摘要： A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated based on decoded first and second addresses. In addition, the decoder includes first and second shift registers respectively coupled to the redundant first and second wordlines, where each is configured to respectively activate the redundant first and second wordlines when the first or second wordlines contain a defect. In addition, a method of selecting wordlines for use in wordline/bitline redundancy control and a wordline decoder having redundancy control capabilities are also disclosed.
摘要翻译：公开了一种用于字线/位线冗余控制的解码器。在一个方面，解码器包括分别耦合到冗余第一和第二字线的第一和第二字线，其中第一和第二字线被配置为基于经解码的第一和第二地址被激活。此外，解码器包括分别耦合到冗余第一和第二字线的第一和第二移位寄存器，其中每个被配置为当第一或第二字线包含缺陷时分别激活冗余第一和第二字线。此外，还公开了一种用于字线/位线冗余控制中使用的字线的方法和具有冗余控制能力的字线解码器。

36. 发明授权

US06826110B2 Cell circuit for multiport memory using decoder 失效
标题翻译：使用解码器的多端口存储器的单元电路
公开(公告)号：US06826110B2
公开(公告)日：2004-11-30
申请号：US10273567
申请日：2002-10-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.
摘要翻译：在多端口存储器阵列的存储器块中提供用于具有减少读取字线数量的数据读出的改进的单元电路。通过在读取的字线和单元电路中的多路复用器之间使用解码器来显着减少读取字线的数量。存储块具有多个地址输入并存储多个写入数据信号。在单元电路中，解码器接收地址输入的子集作为解码器输入并输出多个选择信号。复用器耦合到解码器以接收选择信号，并且基于选择信号选择写入数据信号之一。此外，读取的字线被耦合到解码器，用于将地址输入的子集携带到解码器。

37. 发明授权

US06430672B1 Method for performing address mapping using two lookup tables 失效
标题翻译：使用两个查找表执行地址映射的方法
公开(公告)号：US06430672B1
公开(公告)日：2002-08-06
申请号：US09617829
申请日：2000-07-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Osamu Takahashi , Jan van Lunteren
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Osamu Takahashi , Jan van Lunteren
IPC分类号： G06F1210
CPC分类号： G06F12/0607 , G06F12/0292
摘要： A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective bank number. A block address portion of a physical address is translated to a corresponding bank number and an associated internal bank address. The bank number is formed by concatenating an output from a first lookup table and an output from a second lookup table. The output from the first lookup table is obtained by a first and a second segments of the block address portion, while the output from the second lookup table is obtained by a third and a fourth segments of the block address portion. Data stored in a specific location within the memory banks can be accessed by the bank number and the associated internal bank address.
摘要翻译：公开了一种用于对计算机系统内的存储器执行地址映射的方法。存储器组织在多个存储体中，并且每个存储体由相应的存储体号标识。物理地址的块地址部分被转换为对应的银行号码和相关联的内部银行地址。通过连接来自第一查找表的输出和来自第二查找表的输出来形成库号。来自第一查找表的输出由块地址部分的第一和第二段获得，而来自第二查找表的输出由块地址部分的第三和第四段获得。可以通过银行号码和相关联的内部银行地址访问存储在存储体中的特定位置的数据。

38. 发明授权

US06294929B1 Balanced-delay programmable logic array and method for balancing programmable logic array delays 有权
标题翻译：平衡延迟可编程逻辑阵列和平衡可编程逻辑阵列延迟的方法
公开(公告)号：US06294929B1
公开(公告)日：2001-09-25
申请号：US09443205
申请日：1999-11-18
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Jaehong Park , Stephen Douglas Posluszny , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Jaehong Park , Stephen Douglas Posluszny , Osamu Takahashi
IPC分类号： H03K19177
CPC分类号： H03K19/17712
摘要： Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.
摘要翻译：平衡延迟可编程逻辑阵列和用于平衡可编程逻辑阵列延迟的方法在采用可编程逻辑的电路中提供改进的性能。通过将晶体管添加到不构成逻辑实现的一部分的编程平面，可以平衡每个输入逻辑线上的电容，从而大大减少进入最终逻辑门的信号之间的偏移。这提供了可编程逻辑阵列，可以在以前禁止偏移的应用中实现异步逻辑，并进一步提高了同步逻辑中的状态评估的可靠性。

39. 发明授权

US06172920B2 Data transfer using two-stage bit switch in memory circuit 有权
标题翻译：在存储器电路中使用两级位开关进行数据传输
公开(公告)号：US06172920B2
公开(公告)日：2001-01-09
申请号：US09498087
申请日：2000-02-04
申请人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C712
CPC分类号： G11C7/06 , G11C7/1048 , G11C7/12
摘要： A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch. The data lines are precharged then selectively discharged through source-to-drain paths of the transistors of the first and second stage bit switches.
摘要翻译：用于在存储器电路中读取数据操作的数据传输电路采用两级位开关。来自存储单元阵列的真实和补充位线耦合到第一级位开关中的一对晶体管的栅极。因此，来自位线的数据被转移到没有DC连接的一对读数据节点，因此避免了电荷共享。此外，这允许在没有位线的完全逻辑电平摆幅的情况下提取数据，因此提供更快的操作。来自数据节点的数据通过由定时输入激活的第二级位开关传送到一对数据线。位线上的差分电压由读出放大器增强，并且使用第一级位开关也可以将位线预充电至逻辑电平的一半，加速操作; 该读出放大器在第二级位开关的定时输入之前被激活。数据线被预充电，然后通过第一和第二级位开关的晶体管的源极到漏极路径选择性地放电。

40. 发明授权

US09913996B2 Three-dimensional image capture system and particle beam therapy system 有权
公开(公告)号：US09913996B2
公开(公告)日：2018-03-13
申请号：US14419393
申请日：2012-11-05
申请人： Osamu Takahashi
发明人： Osamu Takahashi
IPC分类号： A61N5/10 , G01B11/10 , G01B11/00 , G01B11/24
CPC分类号： A61N5/1049 , A61N5/1039 , A61N5/1043 , A61N2005/1059 , A61N2005/1074 , A61N2005/1087 , A61N2005/1094 , G01B11/002 , G01B11/10 , G01B11/24
摘要： According to a three-dimensional image capture system of the invention, it includes a three-dimensional measuring device that is placed on a top board and performs image-capturing of a patient to thereby generate three-dimensional-image data, and a three-dimensional-image processing device that generates from the three-dimensional-image data, a three-dimensional image associated with a reference coordinate system with reference to the top board or a floor of a room, and that displays the three-dimensional image. The three-dimensional-image processing device includes a position-information extraction unit that takes a correlation between the reference coordinate system and three-dimensional position information of the patient in the three-dimensional-image data to thereby generate reference-coordinate-system position information of the patient based on the reference coordinate system, and a display unit that displays the three-dimensional image, wherein the display unit displays a reference image and an observed image that are the three-dimensional images captured at different timings.

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