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1. 发明授权

US06175535B1 Cycle control circuit for extending a cycle period of a dynamic memory device subarray 失效
标题翻译：循环控制电路，用于延长动态存储器件子阵列的周期周期
公开(公告)号：US06175535B1
公开(公告)日：2001-01-16
申请号：US09490405
申请日：2000-01-24
申请人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C8/06
摘要： A cycle control circuit for use with a memory device subarray and method of operation thereof. The cycle control circuit includes a previous address buffer for storing a last accessed address of the subarray and an address comparator for comparing a current requested address with the last accessed address in the previous address buffer. The cycle control circuit also includes a cycle counter, coupled to the address comparator, that receives a control signal generated by the address comparator and, in response thereto, modifies a reset operation of the subarray. In another aspect, the method includes applying an address to the subarray and generating control signals for the subarray to produce a data output in response to the address. After producing the data output, the applied address is stored. Next, a new address is received and the new address is compared to the stored address. In response to the stored and new addresses being the same, the reset operation of the subarray is modified to again generate the data output in a shorter period of time.
摘要翻译：一种与存储器件子阵列一起使用的循环控制电路及其操作方法。周期控制电路包括用于存储子阵列的最后访问地址的先前地址缓冲器和用于将当前请求地址与先前地址缓冲器中的最后访问地址进行比较的地址比较器。循环控制电路还包括耦合到地址比较器的周期计数器，其接收由地址比较器产生的控制信号，并响应于此，修改子阵列的复位操作。在另一方面，该方法包括将地址应用于子阵列，并产生用于子阵列的控制信号以产生响应于该地址的数据输出。产生数据输出后，存储应用的地址。接下来，接收到新地址，并将新地址与存储的地址进行比较。响应于存储的和新的地址相同，子阵列的复位操作被修改以在更短的时间段内再次产生数据输出。

2. 发明授权

US06172920B2 Data transfer using two-stage bit switch in memory circuit 有权
标题翻译：在存储器电路中使用两级位开关进行数据传输
公开(公告)号：US06172920B2
公开(公告)日：2001-01-09
申请号：US09498087
申请日：2000-02-04
申请人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C712
CPC分类号： G11C7/06 , G11C7/1048 , G11C7/12
摘要： A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch. The data lines are precharged then selectively discharged through source-to-drain paths of the transistors of the first and second stage bit switches.
摘要翻译：用于在存储器电路中读取数据操作的数据传输电路采用两级位开关。来自存储单元阵列的真实和补充位线耦合到第一级位开关中的一对晶体管的栅极。因此，来自位线的数据被转移到没有DC连接的一对读数据节点，因此避免了电荷共享。此外，这允许在没有位线的完全逻辑电平摆幅的情况下提取数据，因此提供更快的操作。来自数据节点的数据通过由定时输入激活的第二级位开关传送到一对数据线。位线上的差分电压由读出放大器增强，并且使用第一级位开关也可以将位线预充电至逻辑电平的一半，加速操作; 该读出放大器在第二级位开关的定时输入之前被激活。数据线被预充电，然后通过第一和第二级位开关的晶体管的源极到漏极路径选择性地放电。

3. 发明申请

US20050174099A1 Current drive circuit, light emitting element drive circuit and digital-analog converter 失效
标题翻译：电流驱动电路，发光元件驱动电路和数模转换器
公开(公告)号：US20050174099A1
公开(公告)日：2005-08-11
申请号：US11019944
申请日：2004-12-23
申请人： Manabu Ohkubo , Masayuki Ozasa
发明人： Manabu Ohkubo , Masayuki Ozasa
IPC分类号： H01L33/00 , G05F3/16 , G05F3/26 , H03K17/78 , H03M1/74
CPC分类号： H03M1/745 , G05F3/262
摘要： A first current mirror circuit that operates at the time of a rise in a first signal is connected to a current source, a second current mirror circuit that operates at the time of a rise in the first signal is connected to the first current mirror circuit, and a third current mirror circuit that operates at the time of a rise in a second signal is respectively connected to the current source and the point of connection between the first current mirror circuit and the second current mirror circuit. A pulse generation circuit for generating first and second signals from an external signal is provided. The second signal rises in sync with the first signal, and falls before the first signal.
摘要翻译：在第一信号上升时工作的第一电流镜电路连接到电流源，在第一信号上升时工作的第二电流镜电路连接到第一电流镜电路，并且在第二信号的上升时工作的第三电流镜电路分别连接到电流源和第一电流镜电路和第二电流镜电路之间的连接点。提供了用于从外部信号产生第一和第二信号的脉冲发生电路。第二信号与第一信号同步上升，并且落在第一信号之前。

4. 发明授权

US06683335B2 Gate array layout for interconnect 失效
标题翻译：门阵列布局用于互连
公开(公告)号：US06683335B2
公开(公告)日：2004-01-27
申请号：US09887821
申请日：2001-06-22
申请人： Naohisa Hatani , Manabu Ohkubo
发明人： Naohisa Hatani , Manabu Ohkubo
IPC分类号： H01L2710
CPC分类号： H01L27/11803
摘要： In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.
摘要翻译：在具有沿着第一轴的PFET和NFET的相邻线的栅极阵列中，PFET和/或NFET的一些栅极延伸到阱之间并且沿着晶体管的第一（x）轴沿着轴重叠的区域，因此第n晶体管的扩展栅极，（n-1）非延迟晶体管的栅极和相反极性的第（n-1）非延迟晶体管的栅极沿着垂直于（y）的轴线（y）到第一轴。在矩形布局中，右上方晶体管（具有扩展栅极）通过沿着y轴的短连接连接到左下方晶体管。

5. 发明授权

US06337646B1 Digital to analog converter with nonlinear error compensation 有权
标题翻译：具有非线性误差补偿的数模转换器
公开(公告)号：US06337646B1
公开(公告)日：2002-01-08
申请号：US09422635
申请日：1999-10-21
申请人： Naohisa Hatani , Manabu Ohkubo
发明人： Naohisa Hatani , Manabu Ohkubo
IPC分类号： H03M106
CPC分类号： H03M1/0612 , H03M1/785
摘要： To provide a D/A converter and a D/A converting method in which a nonlinear error of an analog output obtained in accordance with a digital input can be decreased without using any specific analog process. An n-bit D/A converter (2) includes: correction signal generating means (4) for generating an m-bit digital correction signal (wherein m is a positive integer) in accordance with an n-bit digital input signal D (wherein n is a positive integer of 2 or more); and D/A conversion means (6) for converting an (n+m)-bit digital signal consisting of the n-bit input signal D and the m-bit correction signal into an analog signal.
摘要翻译：提供D / A转换器和D / A转换方法，其中可以在不使用任何特定的模拟处理的情况下减少根据数字输入获得的模拟输出的非线性误差。一个n位D / A转换器（2 ）包括：根据n位数字输入信号D（其中n是2或更大的正整数）产生m位数字校正信号（其中m是正整数）的校正信号发生装置（4） ; 以及用于将由n位输入信号D和m位校正信号组成的（n + m）位数字信号转换为模拟信号的D / A转换装置（6）。

6. 发明授权

US07362142B2 Current source apparatus, light-emitting-device apparatus and digital-analog converting apparatus 失效
标题翻译：电流源装置，发光装置装置和数模转换装置
公开(公告)号：US07362142B2
公开(公告)日：2008-04-22
申请号：US11003399
申请日：2004-12-06
申请人： Masayuki Ozasa , Manabu Ohkubo
发明人： Masayuki Ozasa , Manabu Ohkubo
IPC分类号： H03K5/22
CPC分类号： H03F3/345 , H03K17/04123
摘要： A current source apparatus includes a first MOS transistor having a drain serving as current input terminals with the gate connected to the drain, a first switch connected to the source of the first MOS transistor, a second MOS transistor having a drain serving as a current output terminal, a second switch connected to the source of the second MOS transistor, a third switch having one end connected to the gate of the first MOS transistor, and the other end connected to the gate of the second MOS transistor, and a drive circuit which controls the second switch and the third switch.
摘要翻译：电流源装置包括：第一MOS晶体管，具有用作栅极连接到漏极的电流输入端的漏极，连接到第一MOS晶体管的源极的第一开关，具有漏极作为电流输出的第二MOS晶体管端子，连接到第二MOS晶体管的源极的第二开关，具有连接到第一MOS晶体管的栅极的一端和与第二MOS晶体管的栅极连接的另一端的第三开关，以及驱动电路，控制第二开关和第三开关。

7. 发明授权

US07064696B2 Current drive circuit, light emitting element drive circuit and digital-analog converter 失效
标题翻译：电流驱动电路，发光元件驱动电路和数模转换器
公开(公告)号：US07064696B2
公开(公告)日：2006-06-20
申请号：US11019944
申请日：2004-12-23
申请人： Manabu Ohkubo , Masayuki Ozasa
发明人： Manabu Ohkubo , Masayuki Ozasa
IPC分类号： H03M1/00
CPC分类号： H03M1/745 , G05F3/262
摘要： A first current mirror circuit that operates at the time of a rise in a first signal is connected to a current source, a second current mirror circuit that operates at the time of a rise in the first signal is connected to the first current mirror circuit, and a third current mirror circuit that operates at the time of a rise in a second signal is respectively connected to the current source and the point of connection between the first current mirror circuit and the second current mirror circuit. A pulse generation circuit for generating first and second signals from an external signal is provided. The second signal rises in sync with the first signal, and falls before the first signal.
摘要翻译：在第一信号上升时工作的第一电流镜电路连接到电流源，在第一信号上升时工作的第二电流镜电路连接到第一电流镜电路，并且在第二信号的上升时工作的第三电流镜电路分别连接到电流源和第一电流镜电路和第二电流镜电路之间的连接点。提供了用于从外部信号产生第一和第二信号的脉冲发生电路。第二信号与第一信号同步上升，并且落在第一信号之前。

8. 发明申请

US20050127988A1 Current source apparatus, light-emitting-device apparatus and digital-analog converting apparatus 失效
标题翻译：电流源装置，发光装置装置和数模转换装置
公开(公告)号：US20050127988A1
公开(公告)日：2005-06-16
申请号：US11003399
申请日：2004-12-06
申请人： Masayuki Ozasa , Manabu Ohkubo
发明人： Masayuki Ozasa , Manabu Ohkubo
IPC分类号： G05F1/10 , H03F3/345 , H03F3/45 , H03K17/0412 , H03K17/78 , H03M1/68
CPC分类号： H03F3/345 , H03K17/04123
摘要： A current source apparatus includes a first MOS transistor having a drain serving as current input terminals with the gate connected to the drain, a first switch connected to the source of the first MOS transistor, a second MOS transistor having a drain serving as a current output terminal, a second switch connected to the source of the second MOS transistor, a third switch having one end connected to the gate of the first MOS transistor, and the other end connected to the gate of the second MOS transistor, and a drive circuit which controls the second switch and the third switch.
摘要翻译：电流源装置包括：第一MOS晶体管，具有用作栅极连接到漏极的电流输入端的漏极，连接到第一MOS晶体管的源极的第一开关，具有漏极作为电流输出的第二MOS晶体管端子，连接到第二MOS晶体管的源极的第二开关，具有连接到第一MOS晶体管的栅极的一端和与第二MOS晶体管的栅极连接的另一端的第三开关，以及驱动电路，控制第二开关和第三开关。

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