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31. 发明授权

US06365471B1 Method for producing PMOS devices 有权
标题翻译：制造PMOS器件的方法
公开(公告)号：US06365471B1
公开(公告)日：2002-04-02
申请号：US09336871
申请日：1999-06-18
申请人： Coming Chen , Sun-Jay Chang
发明人： Coming Chen , Sun-Jay Chang
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes providing a semiconductor substrates and the formation of a gate oxider layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, a pattern is transferred onto the photoresist layer after being put through an exposure and a development. Furthermore, the gate layer and the oxide layer are then etched using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin silicon nitride layer is grown utilizing RTCVD processing. Thereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A silicon oxide layer is deposited using LPCVD, and forming spacers by etching the silicon oxide layer. Next, a heavy doping of boron ions proceeds, as well as an annealing process. The thin silicon nitride layer is etched using diluted phosphoric acid solution. The final stage is the formulation of metal silicides.
摘要翻译：公开了一种防止硼分离和扩散形成PMOS器件的方法。该方法包括在半导体衬底的顶部提供半导体衬底和形成栅极氧化物层以及栅极层。接下来，在栅极层的顶表面上形成光致抗蚀剂层，此外，在曝光和显影之后，将图案转印到光致抗蚀剂层上。此外，然后使用光致抗蚀剂层作为掩模蚀刻栅极层和氧化物层，之后除去光致抗蚀剂层。接下来，利用RTCVD处理生长薄氮化硅层。此后，通过进行离子注入形成硼离子浅结的高掺杂漏极区。使用LPCVD沉积氧化硅层，并通过蚀刻氧化硅层形成间隔物。接下来，进行硼离子的重掺杂，以及退火工艺。使用稀释的磷酸溶液蚀刻薄的氮化硅层。最后阶段是金属硅化物的配方。

32. 发明授权

US06323105B1 Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure 失效
标题翻译：用于制造包括浅沟槽隔离结构和局部氧化隔离结构的隔离结构的方法
公开(公告)号：US06323105B1
公开(公告)日：2001-11-27
申请号：US09188822
申请日：1998-11-09
申请人： Coming Chen , Tony Lin
发明人： Coming Chen , Tony Lin
IPC分类号： H01L2176
CPC分类号： H01L21/76202 , H01L21/763
摘要： A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer. The hard material layer is removed to form the isolation structure of the invention.
摘要翻译：提供了一种通过组合STI工艺和局部氧化（LOCAS）工艺的使用来制造浅沟槽隔离（STI）结构的方法。该方法包括在衬底上形成第一衬里氧化物层，在其上形成图案化的硬质材料层。在硬质材料层的每个侧壁上形成有硬质隔离物。在除了硬隔离物和硬质材料层之外的基板上形成LOCOS结构。然后，去除硬质间隔物以暴露衬底上的衬垫氧化物的一部分。在LOCOS结构的每一侧的基板中形成沟槽。在沟槽的内表面上形成保形第二衬垫氧化物层。沟槽填充有表面高于衬底表面的多晶硅层。进行第二热处理以氧化多晶硅层，以便合并LOCOS结构以覆盖多晶硅层的表面。去除硬质材料层以形成本发明的隔离结构。

33. 发明授权

US06232161B1 Method for forming a dummy active pattern 有权
标题翻译：用于形成虚拟活动图案的方法
公开(公告)号：US06232161B1
公开(公告)日：2001-05-15
申请号：US09211087
申请日：1998-12-15
申请人： Coming Chen , Water Lur
发明人： Coming Chen , Water Lur
IPC分类号： H01L218238
CPC分类号： H01L21/76229
摘要： A method for fabricating a mask comprises a first pattern in respective of active areas, and a second pattern in respective of dummy active areas. After removing the first pattern, the profiles of the dummy active areas are enlarged. The N-well boundary and the P-well boundary of the second pattern is respectively shielded to form a first composed pattern and a second composed pattern comprising the larger dummy active areas and a shielding pattern. The dummy active areas on the substrate are shielded by the patterns of the embodiment during the process of ion implantation. Thus the resistivity of the dummy active areas is increased, whereby the parasitic capacitance can be prevented from being too large and affecting the performance of the devices.
摘要翻译：一种制造掩模的方法包括有效区域中的第一图案和虚拟有效区域中的第二图案。在去除第一图案之后，虚拟有源区域的轮廓被放大。分别屏蔽第二图案的N阱边界和P阱边界以形成第一组合图案和包括较大虚拟有源区和屏蔽图案的第二组合图案。在离子注入过程中，衬底上的虚拟有源区被本实施例的图案屏蔽。因此，虚拟有源区的电阻率增加，从而可以防止寄生电容太大并且影响器件的性能。

34. 发明授权

US06177332B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06177332B1
公开(公告)日：2001-01-23
申请号：US09208624
申请日：1998-12-08
申请人： Coming Chen , Jih-Wen Chou
发明人： Coming Chen , Jih-Wen Chou
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.
摘要翻译：描述了制造浅沟槽隔离的方法。该方法包括提供具有衬垫氧化物层，掩模层和沟槽的衬底的步骤，其中沟槽穿过掩模层和焊盘氧化物层并进入衬底。衬底氧化物层形成在衬底中的沟槽的侧壁的一部分上。在沟槽中形成与衬底和衬垫氧化物层之间的界面相同的表面水平的硅层，并且在硅层上形成绝缘层。

35. 发明授权

US6136713A Method for forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US6136713A
公开(公告)日：2000-10-24
申请号：US165608
申请日：1998-10-02
申请人： Coming Chen , Jenn Tsao , Water Lur
发明人： Coming Chen , Jenn Tsao , Water Lur
IPC分类号： H01L21/76 , H01L21/3205 , H01L21/762 , H01L21/461
CPC分类号： H01L21/76229
摘要： A method for forming a shallow trench isolation (STI) structure adds an etching back process to a conventional method which only uses a chemical mechanical process (CMP) process to accomplish the STI structure. In the method of the invention, the CMP process preliminarily planarizes a substrate to remove an insulation layer above the trench and uses the etching back process to accomplish the STI structure.
摘要翻译：用于形成浅沟槽隔离（STI）结构的方法将常规方法添加了回蚀刻工艺，该方法仅使用化学机械工艺（CMP）工艺来实现STI结构。在本发明的方法中，CMP工艺预先对衬底进行平面化，以除去沟槽上方的绝缘层，并使用蚀刻返回工艺来实现STI结构。

36. 发明授权

US6133083A Method to fabricate embedded DRAM 有权
标题翻译：制造嵌入式DRAM的方法
公开(公告)号：US6133083A
公开(公告)日：2000-10-17
申请号：US218543
申请日：1998-12-22
申请人： Tony Lin , Coming Chen , Jenn Tsao
发明人： Tony Lin , Coming Chen , Jenn Tsao
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/8244
CPC分类号： H01L27/10894 , H01L27/10888
摘要： A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate. A third contact hole is formed in the first dielectric layer and the second dielectric layer to expose the second source/drain region. A capacitor is formed to electrically couple with the second source/drain region through the third contact hole.
摘要翻译：一种用于制造嵌入式DRAM的方法。提供具有存储电路区域和逻辑电路区域的衬底。第一栅极，第一源极/漏极区域和第二源极/漏极区域形成在存储器电路区域中。第二栅极和第三源极/漏极区域形成在逻辑电路区域中。第一电介质层形成在衬底上。在第一电介质层中，形成第一接触孔以暴露第一源极/漏极区域，并且形成第二接触孔以暴露第二栅极和第三源极/漏极区域。形成位线，以通过第一接触孔与第一源极/漏极区域电耦合。局部互连形成为通过第二接触孔与第二栅极和第三源极/漏极区域电耦合。第二介质层形成在衬底上。在第一电介质层和第二电介质层中形成第三接触孔以露出第二源/漏区。形成电容器以通过第三接触孔与第二源极/漏极区域电耦合。

37. 发明授权

US6083827A Method for fabricating local interconnect 失效
标题翻译：制造局部互连的方法
公开(公告)号：US6083827A
公开(公告)日：2000-07-04
申请号：US212084
申请日：1998-12-15
申请人： Tony Lin , Coming Chen , Wen-Kuan Yeh
发明人： Tony Lin , Coming Chen , Wen-Kuan Yeh
IPC分类号： H01L21/321 , H01L21/336 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , H01L21/3212 , H01L29/66545
摘要： A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.
摘要翻译：一种用于制造局部互连的方法。在所提供的衬底上形成具有栅极氧化物层，栅极多晶硅层和覆盖层的栅极。在栅极的侧壁上形成间隔物，在衬底中形成源/漏区。平坦化介电层形成在衬底上以露出盖层。电介质层的一部分和栅极一侧上的间隔物被去除以形成开口，从而暴露出源极/漏极区域。通过去除盖层将开口转变成局部互连开口。通过在局部互连开口中形成导电层形成局部互连。

38. 发明授权

US6015755A Method of fabricating a trench isolation structure using a reverse mask 有权
标题翻译：使用反向掩模制造沟槽隔离结构的方法
公开(公告)号：US6015755A
公开(公告)日：2000-01-18
申请号：US162576
申请日：1998-09-29
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/762 , H01L21/00
CPC分类号： H01L21/76229
摘要： A method for fabricating trench isolation structures using the reverse mask is described. The method of using a reverse mask to fabricate trench isolation structures includes providing a semiconductor substrate having a first trench and a second trench in the substrate. The first trench has a width smaller than a fixed value, while the second trench has a width larger than the fixed value, the fixed value being, for example, about 0.7 .mu.m. Thereafter, a conformal insulating layer is formed over the first trench and the second trench. Next, a reverse mask layer is formed over the conformal insulating layer, and then the reverse mask layer is patterned. The reverse mask layer is patterned selectively. For example, only the region directly above the second trench is covered by the reverse mask. The region directly above the first trench is exposed. Subsequently, using the patterned reverse mask layer as a mask, a portion of the conformal insulating layer is etched away forming a residual conformal insulating layer underneath the reverse mask layer. Thereafter, the reverse mask layer is removed exposing protruding insulating structures. Finally, the regions of the conformal insulating layer protruding above the semiconductor substrate are polished.
摘要翻译：描述了使用反向掩模制造沟槽隔离结构的方法。使用反向掩模制造沟槽隔离结构的方法包括提供在衬底中具有第一沟槽和第二沟槽的半导体衬底。第一沟槽具有小于固定值的宽度，而第二沟槽的宽度大于固定值，固定值例如为约0.7μm。此后，在第一沟槽和第二沟槽之上形成保形绝缘层。接下来，在保形绝缘层上形成反向掩模层，然后对反向掩模层进行图案化。反向掩模层被选择性地图案化。例如，只有第二沟槽正上方的区域被反掩模覆盖。暴露第一沟槽正上方的区域。随后，使用图案化反向掩模层作为掩模，保护绝缘层的一部分被蚀刻掉，在反掩膜层下面形成残留的保形绝缘层。此后，去除暴露的绝缘结构的反面掩模层。最后，抛光在半导体衬底上突出的保形绝缘层的区域。

39. 发明授权

US5958795A Chemical-mechanical polishing for shallow trench isolation 失效
标题翻译：化学机械抛光用于浅沟槽隔离
公开(公告)号：US5958795A
公开(公告)日：1999-09-28
申请号：US75597
申请日：1998-05-11
申请人： Coming Chen , Juan-Yuan Wu , Water Lur
发明人： Coming Chen , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/463
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a plurality of active regions, including a large active region and a small active region, is provided. A silicon nitride layer is formed on the substrate. A shallow trench is formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trench is filled therewith. A partial reverse active mask is formed on the oxide layer, so that the oxide layer on a central part of the large active region is exposed. Whereas, the oxide layer on an edge part of the large active region and on the small active region are covered by the partial reverse active mask. The oxide layer is etched with the silicon nitride layer as a stop layer, using the partial reverse active mask as a mask. The oxide layer is planarized until the oxide layer within the shallow trench has a same level as the silicon nitride layer.
摘要翻译：用于形成浅沟槽隔离的化学机械抛光方法。提供具有多个有源区的基板，其包括大的有源区和小的有源区。在衬底上形成氮化硅层。在活性区域之间形成浅沟槽。在衬底上形成氧化物层，以便填充浅沟槽。在氧化物层上形成部分反向有源掩模，使大面积活性区域的中央部分的氧化物层露出。而大的有源区域的边缘部分和小的有源区域上的氧化物层被部分反向有源掩模覆盖。使用部分反向活性掩模作为掩模，用氮化硅层作为停止层蚀刻氧化物层。氧化层被平坦化，直到浅沟槽内的氧化物层具有与氮化硅层相同的水平。

40. 发明授权

US5950090A Method for fabricating a metal-oxide semiconductor transistor 失效
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US5950090A
公开(公告)日：1999-09-07
申请号：US193217
申请日：1998-11-16
申请人： Coming Chen , Tony Lin , Jih-Wen Chou
发明人： Coming Chen , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/76224 , H01L29/66545 , H01L29/41775
摘要： A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.
摘要翻译：提供一种用于制造MOS晶体管器件的方法。该方法包括在半导体衬底上顺序形成氧化物层，多晶硅层和覆盖层。对氧化物层，多晶硅层，盖层和衬底进行图案化，在衬底中形成沟槽开口。通过用绝缘材料填充开口形成浅沟槽隔离（STI）结构。通过图案化氧化物层，多晶硅层和盖层，在衬底上形成第一级栅极结构。暴露基板表面上方的STI结构的顶部。进行轻离子注入以形成轻掺杂区域。在STI结构的第一级栅极结构的每个侧壁和每个暴露的侧壁上分别形成几个间隔物。执行重离子注入工艺以在第一级栅极结构的每一侧形成可互换的源/漏区。盖层去除以留下开口。导电层形成在衬底上并被平坦化，使得导电层的剩余部分填充开口以用作栅极金属层。导电层的剩余部分还填充可互换的源极/漏极区之间的间隔物之间的自由空间，以形成多个接触插塞。在基板上形成介电层，第二接触插塞分别电耦合到栅极金属层和第一接触插塞。

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