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31. 发明授权

US06423996B1 Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit 有权
标题翻译：在集成电路内制造金属 - 金属电容器的工艺及相应的集成电路
公开(公告)号：US06423996B1
公开(公告)日：2002-07-23
申请号：US09658221
申请日：2000-09-08
申请人： Michel Marty , Herve Jaouen
发明人： Michel Marty , Herve Jaouen
IPC分类号： H01L27108
CPC分类号： H01L28/40
摘要： A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.
摘要翻译：一种用于在集成电路内制造金属 - 金属电容器的工艺包括以下步骤：在下绝缘层的顶部上产生第一金属电极，第二金属电极和电介质层; 以及在所述两个金属电极和所述电介质层的顶部上沉积上绝缘层。集成电路包括绝缘层，位于下绝缘层顶部的第一金属层和位于第一金属层顶部的上绝缘层。电容器包括第一金属电极，第二金属电极和电介质层，其中两个金属电极中的每一个与电介质层的一侧接触。电极和电介质层位于支撑金属化水平（M1）的下绝缘层和覆盖这种金属化水平的上绝缘层之间。

32. 发明授权

US6136640A Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit 失效
标题翻译：在集成电路内制造金属 - 金属电容器的工艺及相应的集成电路
公开(公告)号：US6136640A
公开(公告)日：2000-10-24
申请号：US118499
申请日：1998-07-17
申请人： Michel Marty , Harve Jaouen
发明人： Michel Marty , Harve Jaouen
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/10 , H01L21/8242 , H01L21/20 , H01L27/108
CPC分类号： H01L28/40
摘要： A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the lower insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.
摘要翻译：一种用于在集成电路内制造金属 - 金属电容器的工艺包括以下步骤：在下绝缘层的顶部上产生第一金属电极，第二金属电极和电介质层; 以及在所述两个金属电极和所述电介质层的顶部上沉积上绝缘层。集成电路包括下绝缘层，位于下绝缘层顶部的第一金属层和位于第一金属层顶部的上绝缘层。电容器包括第一金属电极，第二金属电极和电介质层，其中两个金属电极中的每一个与电介质层的一侧接触。电极和电介质层位于支撑金属化水平（M1）的下绝缘层和覆盖该金属化层的上绝缘层之间。

33. 发明授权

US6081030A Semiconductor device having separated exchange means 失效
标题翻译：具有分离的交换装置的半导体装置
公开(公告)号：US6081030A
公开(公告)日：2000-06-27
申请号：US105355
申请日：1998-06-26
申请人： Herve Jaouen , Michel Marty
发明人： Herve Jaouen , Michel Marty
IPC分类号： H01L23/12 , H01F17/00 , H01L23/64 , H01L25/00 , H01L23/34
CPC分类号： H01L23/48 , H01L23/645 , H01L24/73 , H01F17/0006 , H01L2224/16225 , H01L2924/01004 , H01L2924/01033 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/16195 , H01L2924/19103 , H01L2924/19104 , H01L2924/30107
摘要： A semiconductor device having separated exchange mechanism comprises a chip forming an integrated circuit; a connection substrate; device connection points or balls; and at least one exchange mechanism. The connection substrate comprises an external connection mechanism. The device connection points or balls are distributed in the form of a matrix and are located between the juxtaposed faces of the chip and of the connection substrate. The device connection points are connected to the external connection mechanism. The exchange mechanism comprises two parts. The two parts are arranged so as to be separated from each other and capable of exchanging signals between each other, in one or both directions. The first part is physically coupled to the chip. The second part is physically coupled to the connection substrate and is connected to the external connection mechanism.
摘要翻译：具有分离的交换机构的半导体器件包括形成集成电路的芯片; 连接基板; 设备连接点或球; 和至少一个交换机制。连接基板包括外部连接机构。设备连接点或球以矩阵的形式分布并且位于芯片的并置面和连接衬底之间。设备连接点连接到外部连接机构。交换机制包括两部分。这两个部分被布置成彼此分离并且能够在一个或两个方向上彼此之间交换信号。第一部分物理耦合到芯片。第二部分物理耦合到连接基板并连接到外部连接机构。

34. 发明授权

US5815792A Nickel-based superalloys with high temperature stability 失效
标题翻译：具有高温稳定性的镍基超级合金
公开(公告)号：US5815792A
公开(公告)日：1998-09-29
申请号：US689157
申请日：1996-07-30
申请人： Catherine Duquenne , Jean Charles Henri Lautridou , Michel Marty , Michele Soucail , Andre Walder
发明人： Catherine Duquenne , Jean Charles Henri Lautridou , Michel Marty , Michele Soucail , Andre Walder
IPC分类号： C22C19/05 , C22F1/10 , B22F1/00 , B22F5/00 , B22F5/04
CPC分类号： C22F1/10 , C22C19/056
摘要： A nickel-based superalloy possessing good mechanical properties when hot regarding traction, creep and cracking resistance has a chemical composition which comprises, in percentages by weight: Co 14.5 to 15.5 ; Cr 12 to 15 ; Mo 2 to 4.5 : Al 2.5 to 4; Ti 4 to 6; Hf not more than 0.5 ; C 100 to 300 ppm; B 100 to 500 ppm; Zr 200 to 700 ppm; possibly W up to 4.5; and nickel as the remainder. Components made from these alloys have an excellent microstructural stability when operating at temperatures up to 800.degree. C.
摘要翻译：具有良好机械性能的镍基超级合金在热牵引，蠕变和抗裂性方面具有化学组成，其重量百分比：Co 14.5至15.5; Cr 12〜15; Mo 2〜4.5：Al 2.5〜4; Ti 4〜6; Hf不大于0.5; C 100〜300ppm; B 100〜500ppm; Zr 200〜700ppm; 可能W高达4.5; 和镍作为其余部分。当在高达800℃的温度下操作时，由这些合金制成的组分具有优异的微结构稳定性。

35. 发明授权

US4714951A Integrated circuit device which includes a continous layer which consists of conducting portions which are of a silicide of a refractory metal and insulating portions which are of an oxide of the metal 失效
$Integrated circuit device which includes a continous layer which consists of conducting portions which are of a silicide of a refractory metal and insulating portions which are of an oxide of the metal$
标题翻译：集成电路装置，其包括由难熔金属的硅化物的导电部分和金属的氧化物的绝缘部分组成的连续层
公开(公告)号：US4714951A
公开(公告)日：1987-12-22
申请号：US833845
申请日：1986-02-26
申请人： Annie Baudrant , Michel Marty
发明人： Annie Baudrant , Michel Marty
IPC分类号： H01L21/768 , H01L21/28 , H01L21/285 , H01L21/31 , H01L21/316 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/45 , H01L29/78 , H01L27/02 , H01L23/48
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/31683 , H01L29/456 , H01L29/665 , Y10S148/019 , Y10S148/02 , Y10S148/117 , Y10S148/147
摘要： The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.
摘要翻译：本发明涉及一种单晶或多晶硅区域的集成电路，其中源极，栅极和漏极由硅化钽TaSi 2覆盖，而其余部分被部分氧化钽Ta 2 O 5的一部分覆盖，特别是在多晶硅的栅极和厚氧化物和铝合金层与硅化钽接触形成与硅化钽的部分的连接。

36. 发明授权

US08703528B2 Method for forming a back-side illuminated image sensor with a junction insulation 有权
标题翻译：用于形成具有结合绝缘的背面照明图像传感器的方法
公开(公告)号：US08703528B2
公开(公告)日：2014-04-22
申请号：US13445199
申请日：2012-04-12
申请人： Michel Marty , François Roy , Jens Prima
发明人： Michel Marty , François Roy , Jens Prima
IPC分类号： H01L21/00
CPC分类号： H01L27/1464 , H01L27/1463 , H01L27/14683 , H01L27/14687 , H01L27/14689
摘要： A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.
摘要翻译：一种用于形成背面照明图像传感器的方法，包括以下步骤：a）从前表面形成与衬底相反的导电类型的掺杂多晶硅区域，其垂直于正面延伸，进入第一层; b）使衬底从其后表面变薄到达多晶硅区域，同时保持第一层的条带; c）在所述薄化衬底的后表面上沉积与所述衬底相反的导电类型的掺杂非晶硅层; 和d）在能够将非晶硅层转变成结晶层的温度下退火。

37. 发明授权

US08524522B2 Microelectronic device, in particular back side illuminated image sensor, and production process 有权
标题翻译：微电子器件，特别是背面照明图像传感器，以及生产过程
公开(公告)号：US08524522B2
公开(公告)日：2013-09-03
申请号：US12963792
申请日：2010-12-09
申请人： Michel Marty , Didier Dutartre , Francois Roy , Pascal Besson , Jens Prima
发明人： Michel Marty , Didier Dutartre , Francois Roy , Pascal Besson , Jens Prima
IPC分类号： H01L21/00 , H01L21/46 , H01L31/0232 , H01L27/148
CPC分类号： H01L27/14687 , H01L21/2007 , H01L21/30604 , H01L21/76256 , H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14689 , H01L31/028 , H01L31/0312 , H01L31/1812
摘要： A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.
摘要翻译：微电子器件的制造方法包括制造第一半导体衬底，该第一半导体衬底包括存在于衬底的第一侧和第二侧之间的第一层和第二层。第一电子部件和互连部分在第二面上和上方产生。然后通过从第一侧施加的第一选择性蚀刻将衬底减薄，并停止在第一层上，随后在第二层上进行第二选择性蚀刻停止。第二衬底附接在互连部分上。电子部件可以包括通过第二层照射的光电子器件。

38. 发明申请

US20110221035A1 PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING A METAL-INSULATOR-METAL CAPACITOR AND CORRESPONDING INTEGRATED CIRCUIT 审中-公开
标题翻译：用于制造包括金属绝缘体 - 金属电容器和相应的集成电路的集成电路的方法
公开(公告)号：US20110221035A1
公开(公告)日：2011-09-15
申请号：US13034373
申请日：2011-02-24
申请人： Simon Jeannot , Michel Marty , Jean-Christophe Giraudin
发明人： Simon Jeannot , Michel Marty , Jean-Christophe Giraudin
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is fabricated by producing metallization levels in insulating regions, the insulating region being formed of a first material having a first dielectric constant. At least one metal-insulator-metal capacitor is formed by providing metal electrodes in the metallization level, and locally replacing the first material, which is located between the metal electrodes, with a second material having a second dielectric constant greater than the first dielectric constant.
摘要翻译：通过在绝缘区域中产生金属化水平来制造集成电路，绝缘区域由具有第一介电常数的第一材料形成。通过在金属化水平中提供金属电极并且将位于金属电极之间的第一材料局部替换为具有大于第一介电常数的第二介电常数的第二材料，形成至少一个金属 - 绝缘体 - 金属电容器。

39. 发明授权

US07476574B2 Method for forming an integrated circuit semiconductor substrate 有权
标题翻译：集成电路半导体衬底的形成方法
公开(公告)号：US07476574B2
公开(公告)日：2009-01-13
申请号：US11335857
申请日：2006-01-19
申请人： Michel Marty , Grégory Avenier
发明人： Michel Marty , Grégory Avenier
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/76286
摘要： An integrated circuit semiconductor substrate includes an active silicon layer separated from a silicon substrate layer by a buried insulating material layer. The active silicon layer, however, locally includes at least one over-thickness on the side of the buried layer, while maintaining a flat surface state of the semiconductor layer across the integrated circuit. The over-thickness is created by forming a cavity under the active silicon layer in the local area, and then providing the over-thickness by partially filling the cavity at the bottom of the active silicon layer through epitaxial growth. An insulating layer then fills the remaining portions of the cavity.
摘要翻译：集成电路半导体衬底包括通过掩埋绝缘材料层与硅衬底层分离的活性硅层。然而，活性硅层在掩埋层的侧面局部地包括至少一个厚度，同时保持跨越集成电路的半导体层的平坦表面状态。通过在局部区域中的有源硅层下方形成空腔，然后通过外延生长部分填充有源硅层底部的空腔来提供厚度来产生厚度。绝缘层然后填充空腔的剩余部分。

40. 发明授权

US07470559B2 Semiconductor component comprising a buried mirror 有权
标题翻译：半导体元件包括掩埋反射镜
公开(公告)号：US07470559B2
公开(公告)日：2008-12-30
申请号：US11297973
申请日：2005-12-08
申请人： Sébastien Jouan , Michel Marty
发明人： Sébastien Jouan , Michel Marty
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L31/02327 , H01L31/105 , H01L31/1085 , Y02E10/547 , Y02P70/521
摘要： A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.
摘要翻译：在半导体部件中形成掩模反射镜的方法包括以下步骤：形成包括覆盖在基板上的绝缘层上的半导体层的结构; 在半导体层中形成在绝缘层的表面出现的一个或几个开口; 消除绝缘层的一部分，由此形成凹部; 在所述凹部的壁上形成第二薄绝缘层; 以及在所述凹部中在所述第二绝缘层上形成金属层。

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