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31. 发明授权

US06372655B2 Two etchant etch method 失效
公开(公告)号：US06372655B2
公开(公告)日：2002-04-16
申请号：US09836934
申请日：2001-04-17
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

32. 发明申请

US20100304132A1 Controlled vapor deposition of multilayered coatings adhered by an oxide layer 有权
标题翻译：由氧化物层附着的多层涂层的受控气相沉积
公开(公告)号：US20100304132A1
公开(公告)日：2010-12-02
申请号：US12804866
申请日：2010-07-29
申请人： Boris Kobrin , Jeffrey D. Chinn , Romuald Nowak , Richard C. Yi
发明人： Boris Kobrin , Jeffrey D. Chinn , Romuald Nowak , Richard C. Yi
IPC分类号： C23C16/40
CPC分类号： C23C16/0227 , B05D1/185 , B05D1/60 , B05D3/142 , B05D3/145 , B05D7/52 , B05D7/56 , B82Y30/00 , B82Y40/00 , C03C17/42 , C03C23/006 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/402 , C23C16/448 , C23C16/4485 , C23C16/455 , C23C16/45557 , C23C16/56 , Y10T428/12618 , Y10T428/12632 , Y10T428/24 , Y10T428/24355 , Y10T428/24967 , Y10T428/24975 , Y10T428/261 , Y10T428/265 , Y10T428/31663 , Y10T428/31667
摘要： An improved vapor-phase deposition method and apparatus for the application of multilayered films/coatings on substrates is described. The method is used to deposit multilayered coatings where the thickness of an oxide-based layer in direct contact with a substrate is controlled as a function of the chemical composition of the substrate, whereby a subsequently deposited layer bonds better to the oxide-based layer. The improved method is used to deposit multilayered coatings where an oxide-based layer is deposited directly over a substrate and an organic-based layer is directly deposited over the oxide-based layer. Typically, a series of alternating layers of oxide-based layer and organic-based layer are applied.
摘要翻译：描述了一种用于在基底上施加多层膜/涂层的改进的气相沉积方法和装置。该方法用于沉积与衬底直接接触的氧化物基层的厚度作为衬底的化学组成的函数来控制多层涂层，由此随后沉积的层更好地结合到氧化物基层。改进的方法用于沉积多层涂层，其中氧化物基层直接沉积在衬底上，并且基于有机的层直接沉积在氧化物基层上。通常，施加一系列交替层的氧化物基层和基于有机层。

33. 发明申请

US20080206539A1 Durable conformal wear-resistant carbon-doped metal oxide-comprising coating 有权
标题翻译：耐磨保形耐磨碳掺杂金属氧化物涂层
公开(公告)号：US20080206539A1
公开(公告)日：2008-08-28
申请号：US12072086
申请日：2008-02-22
申请人： Boris Kobrin , Romuald Nowak , Jeffrey D. Chinn
发明人： Boris Kobrin , Romuald Nowak , Jeffrey D. Chinn
IPC分类号： H01L21/316 , C23C16/40
CPC分类号： C09D1/00 , B81B3/0075 , C08K3/04 , C08K3/22 , C08K2003/2227 , C23C16/403 , C23C16/405 , C23C16/45525
摘要： The present invention is related to carbon-doped metal oxide films. The carbon-doped metal oxide films provide a low coefficient of friction, for example ranging from about 0.05 to about 0.4. In addition, the carbon-doped metal oxide films applied over a silicon substrate, for example, provide anti-stiction properties, where the measured work of adhesion for a MEMS device cantilever beam coated with the carbon-doped metal oxide film is less than 10 μJ/m2. In addition, the carbon-doped metal oxide films provide unexpectedly good water vapor transmission properties. The carbon content in the carbon-doped metal oxide films ranges from about 5 atomic % to about 20 atomic %.
摘要翻译：本发明涉及碳掺杂金属氧化物膜。碳掺杂的金属氧化物膜提供低摩擦系数，例如约0.05至约0.4。此外，施加在硅衬底上的掺碳金属氧化物膜例如提供抗静电性质，其中测量的涂覆有碳掺杂金属氧化物膜的MEMS器件悬臂梁的粘附力小于10 muJ / m 2。此外，掺杂碳的金属氧化物膜提供出乎意料的良好的水蒸汽透过性能。碳掺杂的金属氧化物膜中的碳含量为约5原子％至约20原子％。

34. 发明授权

US07037854B2 Method for chemical-mechanical jet etching of semiconductor structures 失效
标题翻译：半导体结构的化学机械喷射蚀刻方法
公开(公告)号：US07037854B2
公开(公告)日：2006-05-02
申请号：US10675031
申请日：2003-09-30
申请人： Robert Z. Bachrach , Jeffrey D. Chinn
发明人： Robert Z. Bachrach , Jeffrey D. Chinn
IPC分类号： H01L21/302
CPC分类号： H01L21/6708 , B05B1/20 , B05B7/06 , B05B7/0884
摘要： A chemical-mechanical jet etching method rapidly removes large amounts of material in wafer thinning, or produces large-scale features on a silicon wafer, gallium arsenide substrate, or similar flat semiconductor workpiece, at etch rates in the range of 10–100 microns of workpiece thickness per minute. A nozzle or array of nozzles, optionally including a dual-orifice nozzle, delivers a high-pressure jet of machining etchant fluid to the surface of the workpiece. The machining etchant comprises a liquid or gas, carrying particulate material. The liquid may be a chemical etchant, or a solvent for a chemical etchant, if desired. The areas which are not to be etched may be shielded from the jet by a patterned mask, or the jet may be directed at areas from which material is to be removed, as in wafer thinning or direct writing, depending on the size of the desired feature or etched area.
摘要翻译：化学机械喷射蚀刻方法在硅片，砷化镓衬底或类似的平坦半导体工件上快速去除大量晶片薄化中的材料，或在10-100微米范围内的蚀刻速率下产生大尺寸特征工件厚度每分钟。可选地包括双孔喷嘴的喷嘴或喷嘴阵列将蚀刻剂流体的高压射流输送到工件的表面。加工蚀刻剂包括携带颗粒材料的液体或气体。如果需要，液体可以是化学蚀刻剂或化学蚀刻剂的溶剂。不被蚀刻的区域可以通过图案化掩模与射流屏蔽，或者喷射可以被引导到要从中除去材料的区域，如在晶片变薄或直接写入中，这取决于所需的尺寸特征或蚀刻区域。

35. 发明授权

US06653237B2 High resist-selectivity etch for silicon trench etch applications 失效
公开(公告)号：US06653237B2
公开(公告)日：2003-11-25
申请号：US09893859
申请日：2001-06-27
申请人： Shashank Deshmukh , David Mui , Jeffrey D. Chinn , Dragan V Podlesnik
发明人： Shashank Deshmukh , David Mui , Jeffrey D. Chinn , Dragan V Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/3065 , H01L21/32137
摘要： Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6, at least one fluorocarbon gas, and N2. If desired, Cl2 can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

36. 发明授权

US06605319B1 Use of integrated polygen deposition and RTP for microelectromechanical systems 失效
标题翻译：用于微机电系统的综合多基因沉积和RTP
公开(公告)号：US06605319B1
公开(公告)日：2003-08-12
申请号：US10074277
申请日：2002-02-11
申请人： Jeffrey D. Chinn , Yi-Hsing Chen , Robert Z. Bachrach , John Christopher Moran
发明人： Jeffrey D. Chinn , Yi-Hsing Chen , Robert Z. Bachrach , John Christopher Moran
IPC分类号： C23C1622
CPC分类号： C23C16/52 , C23C16/56
摘要： The method of the invention involves depositing a plurality of thin layers of film, each layer having a thickness ranging from about 500Å to about 2000Å. Low Pressure Chemical Vapor Deposition or other techniques known in the art maybe used to deposit each thin layer of film. The film is polysilicon or silicon-germanium, where the germanium content ranges from about 4% by weight to about 20% by weight germanium. A Rapid Thermal Anneal (“RTA”) is performed on a deposited thin film layer to relieve residual film stress in at least that film layer. The use of RTA rather than furnace annealing permits much shorter annealing times. Optionally, but advantageously, hydrogen may be present during RTA to permit the use of lower processing temperatures, typically about 20% lower relative to a customary anneal. A series of film deposition/rapid thermal anneal cycles is used to produce the desired, nominal total thickness polysilicon film. This method is generally useful for producing polysilicon films in the range of from about 2 microns to about 20 microns.
摘要翻译：本发明的方法包括沉积多层薄膜，各层的厚度范围为约500至约2000。低压化学气相沉积或本领域已知的其它技术可以用于沉积每层薄膜。该膜是多晶硅或硅 - 锗，其中锗含量为约4重量％至约20重量％的锗。在沉积的薄膜层上进行快速热退火（“RTA”）以减轻至少该膜层中的残余膜应力。使用RTA而不是炉退火允许更短的退火时间。可选地，但是有利地，在RTA期间可能存在氢，以允许使用较低的加工温度，相对于常规退火，通常约为20％。使用一系列膜沉积/快速热退火循环来产生所需的标称总厚度多晶硅膜。该方法通常可用于生产在约2微米至约20微米范围内的多晶硅膜。

37. 发明授权

US06599437B2 Method of etching organic antireflection coating (ARC) layers 失效
标题翻译：蚀刻有机抗反射涂层（ARC）层的方法
公开(公告)号：US06599437B2
公开(公告)日：2003-07-29
申请号：US09813392
申请日：2001-03-20
申请人： Oranna Yauw , Meihua Shen , Nicolas Gani , Jeffrey D. Chinn
发明人： Oranna Yauw , Meihua Shen , Nicolas Gani , Jeffrey D. Chinn
IPC分类号： H01L213213
CPC分类号： H01L21/0276 , H01L21/31138
摘要： A two-step method of etching an organic coating layer, in particular, an organic antireflection coating (ARC) layer, is disclosed. During the main etch step, the organic coating layer is etched using a plasma generated from a first source gas which includes a fluorocarbon and a non-carbon-containing, halogen-comprising gas. Etching is performed using a first substrate bias power. During the overetch step, residual organic coating material remaining after the main etch step is removed by exposing the substrate to a plasma generated from a second source gas which includes a chlorine-containing gas and an oxygen-containing gas, and which does not include a polymer-forming gas. The overetch step is performed using a second substrate bias power which is less than the first substrate bias power. The first source gas and first substrate bias power provide a higher etch rate in dense feature areas than in isolated feature areas during the main etch step, whereas the second source gas and second substrate bias power provide a higher etch rate in isolated feature areas than in dense feature areas during the overetch step, resulting in an overall balancing effect.
摘要翻译：公开了蚀刻有机涂层，特别是有机抗反射涂层（ARC）层的两步法。在主蚀刻步骤期间，使用由包括碳氟化合物和非含碳卤素气体的第一源气体产生的等离子体蚀刻有机涂层。使用第一衬底偏置功率进行蚀刻。在过蚀刻步骤期间，通过将衬底暴露于由包含含氯气体和含氧气体的第二源气体产生的等离子体而将主蚀刻步骤后剩余的残留有机涂层材料除去，并且不包括聚合物形成气体。使用小于第一衬底偏置功率的第二衬底偏置功率来执行过蚀刻步骤。在主蚀刻步骤期间，第一源气体和第一衬底偏置功率在致密特征区域中提供比在隔离特征区域中更高的蚀刻速率，而第二源气体和第二衬底偏置功率在隔离特征区域中提供比在在疏浚过程中密集的特征区域，导致整体平衡效果。

38. 发明授权

US06518192B2 Two etchant etch method 失效
公开(公告)号：US06518192B2
公开(公告)日：2003-02-11
申请号：US10013115
申请日：2001-12-07
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

39. 发明授权

US06391788B1 Two etchant etch method 失效
标题翻译：两种蚀刻剂蚀刻方法
公开(公告)号：US06391788B1
公开(公告)日：2002-05-21
申请号：US09513552
申请日：2000-02-25
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
摘要翻译：描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

40. 发明授权

US06372151B1 Storage poly process without carbon contamination 失效
标题翻译：储存聚合工艺无碳污染
公开(公告)号：US06372151B1
公开(公告)日：2002-04-16
申请号：US09362929
申请日：1999-07-27
申请人： Taeho Shin , Nam-Hun Kim , Jeffrey D. Chinn
发明人： Taeho Shin , Nam-Hun Kim , Jeffrey D. Chinn
IPC分类号： B44C122
CPC分类号： H01L21/32137
摘要： The method of present invention etches a layer of polysilicon formed on a substrate disposed within a substrate processing chamber. The method flows an etchant gas including sulfur hexafluoride, an oxygen source and a nitrogen source into the processing chamber and ignites a plasma from the etchant gas to etch the polysilicon formed over the substrate. In a preferred embodiment, the etchant gas consists essentially of SF6, molecular oxygen (O2) and molecular nitrogen (N2). In a more preferred embodiment the etchant gas includes a volume ratio of molecular oxygen to the sulfur hexafluoride of between 0.5:1 and 1:1 inclusive and a volume ratio of the sulfur hexafluoride to molecular nitrogen of between 1:1 and 4:1 inclusive. In an even more preferred embodiment, the volume ratio of O2 to sulfur hexafluoride is between 0.5:1 and 1:1 inclusive and the volume ratio of sulfur hexafluoride to N2 is between 1.5:1 and 2:1 inclusive.
摘要翻译：本发明的方法蚀刻形成在设置在衬底处理室内的衬底上的多晶硅层。该方法将包括六氟化硫，氧源和氮源的蚀刻剂气体流入处理室，并且从蚀刻剂气体点燃等离子体以蚀刻形成在衬底上的多晶硅。在优选的实施方案中，蚀刻剂气体基本上由SF 6，分子氧（O 2）和分子氮（N 2）组成。在更优选的实施方案中，蚀刻剂气体包括分子氧与六氟化硫的体积比在0.5:1至1:1之间，六氟化硫与分子氮的体积比在1:1至4:1之间，包括。在更优选的实施方案中，O 2与六氟化硫的体积比在0.5:1和1:1之间，并且六氟化硫与N 2的体积比在1.5:1和2:1之间。

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