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31. 发明授权

US06312980B1 Programmable triangular shaped device having variable gain 失效
标题翻译：具有可变增益的可编程三角形器件
公开(公告)号：US06312980B1
公开(公告)日：2001-11-06
申请号：US09092827
申请日：1998-06-05
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L2182
CPC分类号： H01L27/108 , G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/528 , H01L27/11 , H01L27/1104 , H01L27/11807 , H01L29/0657 , H01L2924/0002 , Y10S438/965 , H01L2924/00
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

32. 发明授权

US5654563A Microelectronic integrated circuit including triangular semiconductor "or" g 失效
标题翻译：微电子集成电路包括三角半导体“或”门极器件“
公开(公告)号：US5654563A
公开(公告)日：1997-08-05
申请号：US567894
申请日：1995-12-06
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L23/528 , H01L27/088 , H01L29/06 , H01L29/78 , H01L25/00 , H01L29/772
CPC分类号： H01L29/0692 , H01L23/528 , H01L27/088 , H01L29/7831 , H01L2924/0002
摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to vertices of the triangle respectively. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the sides of the triangle. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. One or two of the first to third terminals, rather than the central terminal, can be used for output to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.
摘要翻译：微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。每个装置具有由三角形限定的周边，并且包括形成在周边内的有效区域，形成在有源区域的中心部分中的中心端子，以及形成在与三角形顶点相邻的有源区域中的互连的第一至第三端子分别。第一至第三栅极分别形成在第一至第三端子和中心端子之间，并且具有形成在与三角形的侧面相邻的有源区域外部的触点。为每个器件选择与中心端子和第一至第三端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的OR，NOR ，AND或NAND功能。第一至第三终端中的一个或两个，而不是中心终端，可用于输出以提供与/或逻辑功能。这些设备使用基于六边形几何的三向路由进行互连。

33. 发明授权

US5650653A Microelectronic integrated circuit including triangular CMOS "nand" gate device 失效
标题翻译：微电子集成电路包括三角形CMOS“nand”门极器件
公开(公告)号：US5650653A
公开(公告)日：1997-07-22
申请号：US561107
申请日：1995-11-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L27/092 , H01L27/118 , H01L29/423 , H01L29/78 , H01L29/76 , H01L27/10 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0922 , H01L27/11807 , H01L29/4238 , H01L29/7831
摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a triangular ANY element of a first conductivity type (PMOS or NMOS), and a triangular ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.
摘要翻译：微电子集成电路包括半导体衬底和形成在衬底上的多个CMOS微电子器件。每个器件包括第一导电类型（PMOS或NMOS）的三角形ANY元件和第二导电类型（NMOS或PMOS）的三角形ALL元件，每个ANY和ALL元件都具有多个输入端和输出端电连接。 ANY元素基本上是一个OR元素，ALL元素基本上是AND元素。然而，可以改变ANY和ALL元件的电源连接和导电类型（NMOS或PMOS）的选择，以使器件具有所需的NAND，AND，NOR或OR配置，其中ANY元件作为上拉和ALL元素作为下拉，反之亦然。

34. 发明授权

US5835378A Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip 失效
标题翻译：用于集成电路芯片的电池放置中用于调平互连布线密度的计算机实现的方法
公开(公告)号：US5835378A
公开(公告)日：1998-11-10
申请号：US560834
申请日：1995-11-20
申请人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin , Douglas B. Boyle
发明人： Ranko Scepanovic , James S. Koford , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin , Douglas B. Boyle
IPC分类号： G06F17/50 , G06F9/00 , G06F11/00
CPC分类号： G06F17/5072
摘要： A digital computer includes a processor, a memory and a program which operate in combination for inputting a placement of cells for an integrated circuit chip, and a netlist of wiring nets interconnecting the cells. The placement is divided into a plurality of contiguous regions, and cell densities in the regions are computed in accordance with locations of the cells in the placement. Wiring densities in the regions are computed in accordance with the locations of the cells and the netlist. The shapes of the regions are altered to produce altered regions such that cell densities and wiring densities in the altered regions are more level or uniform. The placement is then altered such that the cells occupy locations in the altered regions which are relative to their locations in the original regions. The porosities of the cells can also be computed and used in the computation of the region shapes. The wiring densities are computed by constructing bounding boxes around the wiring nets, and computing horizontal and vertical total heights and widths of bounding boxes that overlap the regions. The altered shapes are generated by computing optimal sizes for the regions for containing the cells and required interconnect wiring, computing new lengths for edges of the regions, and iteratively recomputing new positions for corners of the regions using a mechanical mass-spring model until the system reaches equilibrium.
摘要翻译：数字计算机包括处理器，存储器和程序，其组合操作用于输入用于集成电路芯片的单元的放置，以及互连单元的布线网的网表。放置被分成多个连续区域，并且根据放置中的单元格的位置来计算区域中的单元密度。根据单元格和网表的位置来计算区域中的布线密度。改变区域的形状以产生改变的区域，使得改变区域中的细胞密度和接线密度更高或均匀。然后改变放置，使得细胞占据相对于它们在原始区域中的位置的改变区域中的位置。还可以计算细胞的孔隙率，并用于计算区域形状。布线密度通过在布线网周围构造边界框，并计算与区域重叠的边界框的水平和垂直总高度和宽度来计算。改变的形状是通过计算用于包含单元的区域和所需的互连布线，计算区域边缘的新长度以及使用机械质量弹簧模型迭代地重新计算区域的角部的新位置而产生的，直到系统达到平衡。

35. 发明授权

US5784287A Physical design automation system and process for designing integrated circuit chips using generalized assignment 失效
标题翻译：物理设计自动化系统和使用广义分配设计集成电路芯片的过程
公开(公告)号：US5784287A
公开(公告)日：1998-07-21
申请号：US536004
申请日：1995-09-29
申请人： Ranko Scepanovic , James S. Koford , Edwin R. Jones , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Ranko Scepanovic , James S. Koford , Edwin R. Jones , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A process for designing an integrated circuit chip s comprises specifying a plurality of regions on the chip in which a plurality of objects are to be placed, such that there are more of the objects than the regions, and specifying penalties for the objects to be placed in the regions respectively. The objects can be microelectronic cells, interconnect wiring segments, etc. An assignment of the objects to the regions is constructed, and a number of objects for movement between the regions is selected. An optimal permutation of movement of the selected number of objects between the regions is computed such that a cost corresponding to the total penalties for the assignment is maximally reduced, and the assignment is modified by moving the selected number of objects through the optimal permutation. The process steps are repeated iteratively such that a maximum number of objects which will produce a maximal reduction in cost is moved during each iteration. The optimal permutation is determined by computing penalty changes for moving the objects between the regions respectively, defining a penalty change scale having a plurality of subintervals, assigning the objects to the penalty change scale in accordance with their penalty changes, and moving the objects which have penalty changes in a number of subintervals having largest values of negative penalty change.
摘要翻译：设计集成电路芯片的过程包括在芯片上指定多个对象要放置的多个区域，使得存在比区域更多的对象，并且指定要放置的对象的处罚分别在区域。物体可以是微电子单元，互连布线段等。构造对象到区域的分配，并且选择用于在区域之间移动的多个对象。计算在区域之间所选择的对象数量的移动的最佳排列，使得对应于分配的总惩罚的成本被最大程度地减少，并且通过移动所选择的对象数量通过最优排列来修改分配。迭代地重复处理步骤，使得在每次迭代期间移动将产生最大成本降低的最大数量的对象。通过计算用于在区域之间移动对象的惩罚变化来确定最优排列，定义具有多个子区间的惩罚改变量表，根据其惩罚改变将对象分配给惩罚改变量表，以及移动具有在具有最大值的负惩罚变化的多个子区间中的惩罚变化。

36. 发明授权

US6038385A Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用“棋盘”和“抖动”优化设计集成电路芯片的过程
公开(公告)号：US6038385A
公开(公告)日：2000-03-14
申请号：US609397
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。针对每个抖动的每个颜色顺序地执行诸如模拟退火的放置改善操作。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。

37. 发明授权

US5971588A Advanced modular cell placement system with optimization of cell neighborhood system 失效
标题翻译：先进的模块化放置系统，优化了小区邻域系统
公开(公告)号：US5971588A
公开(公告)日：1999-10-26
申请号：US672423
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.
摘要翻译：本文提供了一种用于在半导体芯片的表面上提供最佳的单元簇的系统。系统收集预定量的单元，该预定量包含一个中心单元，并且从中心单元分配所有单元的距离值。基于其相关联的距离值将坐标分配给每个小区，并且基于与每个小区相关联的相关小区位置和权重来计算新的小区位置。

38. 发明授权

US5963455A Advanced modular cell placement system with functional sieve optimization technique 失效
标题翻译：先进的模块化电池放置系统，具有功能筛选优化技术
公开(公告)号：US5963455A
公开(公告)日：1999-10-05
申请号：US672936
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimizing placement of a cell on a surface of a semiconductor chip is disclosed herein. The cells may belong to nets and may belong to neighborhoods. The system initially calculates affinities based on repositioning the cell. The system then combines affinities and repositions cells based on these combined affinities. The system then computes a cost function and repeats the combining, repositioning, and computing functions a predetermined number of times.
摘要翻译：本文公开了一种用于优化半导体芯片的表面上的单元的布置的系统。这些小区可能属于网络，可能属于邻居。系统最初基于重新定位单元格计算亲和度。然后，该系统基于这些组合的亲和力结合亲和力和重新定位细胞。然后，系统计算成本函数并重复组合，重新定位和计算功能预定次数。

39. 发明授权

US5892688A Advanced modular cell placement system with iterative one dimensional preplacement optimization 失效
标题翻译：先进的模块化放置系统，具有迭代一维预置位优化
公开(公告)号：US5892688A
公开(公告)日：1999-04-06
申请号：US672335
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for providing an optimal preplacement of cells on a bounded surface of a semiconductor chip is disclosed herein. A percentage of the cells have predetermined interconnections with other cells. The system initially locates the cells on said surface, then computes coordinates for interconnected cells, determines a weight associated with each cell, and calculates a new cell coordinate for each cell based on the coordinates and weights from said determining step.
摘要翻译：本文公开了一种用于在半导体芯片的有界表面上提供单元的最佳预置位的系统。细胞的百分比具有与其他细胞的预定互连。系统首先将单元定位在所述表面上，然后计算互连单元的坐标，确定与每个单元相关联的重量，并且基于来自所述确定步骤的坐标和权重来计算每个单元的新单元坐标。

40. 发明授权

US5872718A Advanced modular cell placement system 失效
标题翻译：先进的模块化放置系统
公开(公告)号：US5872718A
公开(公告)日：1999-02-16
申请号：US672535
申请日：1996-06-28
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.
摘要翻译：本文提供了用于在集成电路芯片的表面上最佳地定位单元的系统。该系统包括构成包含彼此位置相关的元素的多个邻域; 初步评估区域层次的最低水平; 迭代地开发所述表面上的元件的逻辑一维预置位; 执行亲和力驱动的离散预置位优化; 评估是否实现了最高层次的区域层级; 迭代地执行色散驱动弹簧系统来平衡细胞密度和无约束正弦优化; 执行密度调整程序; 迭代优化，同时控制元件密度; 去除元件重叠; 迭代地优化元件之间的期望间隔，调整元件间距和排列元件; 在网格线上定位元素; 并迭代进行功能筛结晶。

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