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31. 发明申请

US20090079027A1 SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM 有权
标题翻译：与SOI嵌入式DRAM兼容的稳定隔离结构
公开(公告)号：US20090079027A1
公开(公告)日：2009-03-26
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

32. 发明申请

US20080248625A1 METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR 审中-公开
公开(公告)号：US20080248625A1
公开(公告)日：2008-10-09
申请号：US12120535
申请日：2008-05-14
申请人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
发明人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
IPC分类号： H01L21/441
CPC分类号： H01L29/945 , H01L28/84 , H01L29/66181
摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

33. 发明授权

US6153474A Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate 失效
标题翻译：在延伸到半导体衬底的沟槽的垂直延伸的侧壁的一部分上可控地形成LOCOS氧化物层的方法
公开(公告)号：US6153474A
公开(公告)日：2000-11-28
申请号：US108619
申请日：1998-07-01
申请人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
发明人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.
摘要翻译：本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。

34. 发明授权

US06066570A Method and apparatus for preventing formation of black silicon on edges of wafers 有权
标题翻译：防止在硅片边缘形成黑色硅的方法和装置
公开(公告)号：US06066570A
公开(公告)日：2000-05-23
申请号：US209413
申请日：1998-12-10
申请人： Dung-Ching Perng , David M. Dobuzinsky , Ting Hao Wang , Klaus Roithner
发明人： Dung-Ching Perng , David M. Dobuzinsky , Ting Hao Wang , Klaus Roithner
IPC分类号： H01L21/302 , H01L21/20 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/316 , H01L21/00
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/30604 , H01L21/3081 , H01L21/31612
摘要： A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.
摘要翻译：根据本发明的通过减少黑硅沉积来提高芯片产量的方法包括以下步骤：提供适于制造半导体芯片的硅晶片，在晶片的整个表面上沉积第一层，去除第一层的一部分以暴露适于形成半导体器件的区域并蚀刻晶片，使得第一层的剩余部分防止蚀刻材料在晶片上的再沉积。一种用于减少黑色硅沉积的半导体组件，包括适于制造半导体芯片的硅晶片，该晶片具有用于形成半导体器件的前表面，后表面和边缘。在晶片上形成用于覆盖背面和边缘的沉积层，从而防止在蚀刻期间在背面和晶片边缘上再沉积硅。

35. 发明授权

US5759746A Fabrication process using a thin resist 失效
标题翻译：使用薄抗蚀剂的制造工艺
公开(公告)号：US5759746A
公开(公告)日：1998-06-02
申请号：US653426
申请日：1996-05-24
申请人： Tsukasa Azuma , Tokuhisa Ohiwa , Tetsuo Matsuda , David M. Dobuzinsky , Katsuya Okumura
发明人： Tsukasa Azuma , Tokuhisa Ohiwa , Tetsuo Matsuda , David M. Dobuzinsky , Katsuya Okumura
IPC分类号： G03F7/11 , G03F7/09 , H01L21/027 , G03F7/26
CPC分类号： G03F7/091 , H01L21/0276 , Y10S430/151 , Y10S438/945 , Y10S438/95
摘要： A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.
摘要翻译：制造工艺包括提供待制造的基板的步骤。然后在基板上形成多层抗反射层。在多层抗反射层上形成厚度小于850纳米的图案化抗蚀剂，并使用图案化的抗蚀剂作为掩模制造基板。

36. 发明授权

US5656535A Storage node process for deep trench-based DRAM 失效
标题翻译：深沟槽DRAM的存储节点处理
公开(公告)号：US5656535A
公开(公告)日：1997-08-12
申请号：US610912
申请日：1996-03-04
申请人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
发明人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
摘要翻译：一种在半导体衬底上制造用于深沟槽DRAM的存储节点的简化方法。该方法包括在衬底的表面中蚀刻沟槽，然后在沟槽的侧壁上形成介电材料层，其顶部部分随后从侧壁去除。接下来，在侧壁的暴露部分上生长一层氧化物。然后从侧壁去除该层氧化物的一部分，以便将氧化层定向到距衬底表面预定的距离。最后，沟槽填充有半导体材料。

37. 发明授权

US5643823A Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures 失效
标题翻译：薄晶体Si3N4衬垫在浅沟槽隔离（STI）结构中的应用
公开(公告)号：US5643823A
公开(公告)日：1997-07-01
申请号：US531844
申请日：1995-09-21
申请人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , J. Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
发明人： Herbert Ho , Erwin Hammerl , David M. Dobuzinsky , J. Herbert Palm , Stephen Fugardi , Atul Ajmera , James F. Moseman , Samuel C. Ramac
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/318 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3105 , H01L21/32 , H01L21/76224 , Y10S148/05
摘要： Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. C. for 60 seconds.
摘要翻译：硅集成电路在浅沟槽隔离（STI）结构中使用氮化硅（Si 3 N 4）的结晶层作为O 2阻挡膜。与沉积的非晶Si3N4相比，晶体Si3N4降低了电子阱的密度。此外，可以沉积更大范围的低压化学气相沉积（LPCVD）Si 3 N 4膜，为厚度可控性提供更大的处理窗口。在720℃至780℃的温度下沉积LPCVD-Si 3 N 4膜。沉积膜处于非晶状态。随后，在1050℃至1100℃下进行纯氮或氨的高温快速热退火60秒。

38. 发明授权

US5204138A Plasma enhanced CVD process for fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜的等离子体增强CVD工艺
公开(公告)号：US5204138A
公开(公告)日：1993-04-20
申请号：US814973
申请日：1991-12-24
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
摘要翻译：公开了一种用于在衬底上制造氟化氮化硅层的等离子体增强化学气相沉积工艺。该方法利用硅烷，全氟硅烷和氮气的混合物来制备具有高共形性和稳定性的膜。混合物中的硅烷和全氟硅烷的体积比为0.05-1。优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。

39. 发明授权

US07893485B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US07893485B2
公开(公告)日：2011-02-22
申请号：US11955913
申请日：2007-12-13
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/792
CPC分类号： H01L29/42352 , H01L21/28282 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元的半导体存储器件，其允许将基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

40. 发明申请

US20100193852A1 EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION 有权
标题翻译：嵌入式DRAM记忆体与附加图案层，用于改进的形成
公开(公告)号：US20100193852A1
公开(公告)日：2010-08-05
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

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