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31. 发明授权

US06539072B1 Delay locked loop circuitry for clock delay adjustment 有权
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US06539072B1
公开(公告)日：2003-03-25
申请号：US09524402
申请日：2000-03-13
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H04L700
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

32. 发明授权

US6157244A Power supply independent temperature sensor 有权
标题翻译：电源独立温度传感器
公开(公告)号：US6157244A
公开(公告)日：2000-12-05
申请号：US170335
申请日：1998-10-13
申请人： Thomas H. Lee , Mark G. Johnson , John C. Holst
发明人： Thomas H. Lee , Mark G. Johnson , John C. Holst
IPC分类号： G01K7/01 , G05F1/10
CPC分类号： G01K7/01
摘要： A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.
摘要翻译：温度传感器与集成电路结合使用适合于制造该器件的制造技术的另一个器件（如微处理器）制造。温度传感器的操作基于使用带隙参考电路的半导体带隙物理学和产生两个测量电压的放大器，其是依赖于温度的电压和与温度无关的电压。温度传感器包括带隙电源电路，其提供非常稳定的驱动温度传感器的电源电压，使得温度传感器产生基本上与电源电压无关的输出信号。

33. 发明授权

US6125157A Delay-locked loop circuitry for clock delay adjustment 失效
标题翻译：用于时钟延迟调整的延迟锁定环路
公开(公告)号：US6125157A
公开(公告)日：2000-09-26
申请号：US795657
申请日：1997-02-06
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0037 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H04L7/0008 , H04L7/0025
摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.
摘要翻译：延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

34. 发明授权

US07039147B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07039147B2
公开(公告)日：2006-05-02
申请号：US10366865
申请日：2003-02-14
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

35. 发明授权

US06545891B1 Modular memory device 有权
标题翻译：模块化存储设备
公开(公告)号：US06545891B1
公开(公告)日：2003-04-08
申请号：US09638334
申请日：2000-08-14
申请人： J. James Tringali , P. Michael Farmwald , Thomas H. Lee , Mark G. Johnson , Derek J. Bosch
发明人： J. James Tringali , P. Michael Farmwald , Thomas H. Lee , Mark G. Johnson , Derek J. Bosch
IPC分类号： G11C502
CPC分类号： G11C5/025 , G11C5/063
摘要： A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.
摘要翻译：模块化存储器件包括支撑元件，包括由支撑元件承载的三维存储器阵列的存储器单元，由支撑元件承载并与存储器单元耦合的器件接口单元，以及由支撑元件承载的电连接器并与设备接口单元耦合。存储器阵列非常适合用作数字媒体的数字媒体存储设备，例如数字文本，数字音乐，数字图像或图像以及数字视频。在所有情况下都不需要设备接口单元。

36. 发明授权

US06515888B2 Low cost three-dimensional memory array 有权
标题翻译：低成本三维存储阵列
公开(公告)号：US06515888B2
公开(公告)日：2003-02-04
申请号：US09928969
申请日：2001-08-13
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , N. Johan Knall
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , N. Johan Knall
IPC分类号： G11C1100
CPC分类号： H01L27/101 , G11C17/16 , H01L27/0688
摘要： A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
摘要翻译：低成本存储单元阵列包括多个垂直堆叠的存储单元层。在一种形式中，每个存储单元的特征在于小的横截面积和小于6.3微安培的读取电流。所得到的存储器阵列具有缓慢的访问时间，并且非常适合于数字媒体存储，其中访问时间要求低，并且与所公开的存储器阵列相关联的显着的成本降低特别有吸引力。在另一种形式中，每个存储器单元包括反熔丝层和二极管部件，其中至少一个二极管部件被重掺杂（掺杂浓度大于1019 / cm3），并且其中读取电流大（高达500mA）。

37. 发明授权

US07283403B2 Memory device and method for simultaneously programming and/or reading memory cells on different levels 失效
标题翻译：用于同时编程和/或读取不同级别的存储单元的存储器件和方法
公开(公告)号：US07283403B2
公开(公告)日：2007-10-16
申请号：US10987091
申请日：2004-11-12
申请人： Mark G. Johnson
发明人： Mark G. Johnson
IPC分类号： G11C7/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

38. 发明授权

US07177183B2 Multiple twin cell non-volatile memory array and logic block structure and method therefor 有权
标题翻译：多个单元非易失性存储器阵列及其逻辑块结构及其方法
公开(公告)号：US07177183B2
公开(公告)日：2007-02-13
申请号：US10675212
申请日：2003-09-30
申请人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
发明人： Roy E. Scheuerlein , Luca Fasoli , Mark G. Johnson
IPC分类号： G11C16/04
CPC分类号： G11C15/046 , G11C8/10 , G11C8/14 , G11C16/10 , G11C16/16
摘要： Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays. Such arrays may be configured as a memory to store data, or configured to perform threshold logic, or configured as a content addressable memory array.
摘要翻译：非常密集的存储单元结构提供了用于实现内存和逻辑功能的新数组结构。示例性非易失性存储器阵列包括被配置为在读取操作模式下在逻辑上相同的第一多个X线，并且每个X线与与至少一个Y线编号的第一Y线组相关联。第一多个X线中的每一个也可以与编号至少一个Y线的第二Y线组相关联。在一些实施例中，第一和第二Y线组可以以读取模式同时选择，并且当这样选择时，它们分别耦合到读出放大器电路的真实和补码输入。这样的Y线组可以仅编号一条Y线，或者可以编号多于一条Y线。可以在2D或3D存储器阵列中使用许多类型的存储单元，例如各种无源元件单元和EEPROM单元。这样的阵列可以被配置为存储数据，或被配置为执行阈值逻辑或被配置为内容可寻址存储器阵列的存储器。

39. 发明授权

US06901549B2 Method for altering a word stored in a write-once memory device 失效
标题翻译：用于改变存储在一次写入存储器件中的字的方法
公开(公告)号：US06901549B2
公开(公告)日：2005-05-31
申请号：US10023200
申请日：2001-12-14
申请人： Roger W. March , Christopher S. Moore , Mark G. Johnson
发明人： Roger W. March , Christopher S. Moore , Mark G. Johnson
IPC分类号： G11C7/10 , G11C7/24 , G11C17/14 , H03M13/00
CPC分类号： G11C17/146 , G11C7/1006 , G11C7/24 , G11C17/14
摘要： The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例提供了一种用于改变存储在一次写入存储器件中的字的方法。在一个优选实施例中，提供了一次写入存储器件，其存储包括多个数据位和多个校正子位的字。通过识别字处于非编程状态的X位，并将X位从未编程状态切换到编程状态来改变该字，其中X足以引入不可校正的错误在这个词中。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

40. 发明授权

US06525949B1 Charge pump circuit 有权
公开(公告)号：US06525949B1
公开(公告)日：2003-02-25
申请号：US09748815
申请日：2000-12-22
申请人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
发明人： Mark G. Johnson , Joseph G. Nolan, III , Matthew P. Crowley
IPC分类号： H02M318
CPC分类号： H02M3/073
摘要： A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

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