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31. 发明申请

US20090198959A1 SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIVE OPERATIONS 失效
标题翻译：可扩展的链路堆栈控制方法，具有全面的支持用于分析操作
公开(公告)号：US20090198959A1
公开(公告)日：2009-08-06
申请号：US12023913
申请日：2008-01-31
申请人： Ronald P. Hall , Michael Lance Karm , David Mui , Albert James Van Norstrand, JR.
发明人： Ronald P. Hall , Michael Lance Karm , David Mui , Albert James Van Norstrand, JR.
IPC分类号： G06F9/315
CPC分类号： G06F9/30134 , G06F9/30054 , G06F9/3806 , G06F9/3842
摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.
摘要翻译：计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。数据处理系统利用推测性推送并从链路堆栈弹出。链路栈包括一组条目，并且每个条目包括一组状态位。第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。第一位被设置为指示第一条指令是有效指令。第二位被设置为指示第一条指令被推测地推到链路栈上。更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。

32. 发明申请

US20090113192A1 DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH 有权
标题翻译：提高短路指令效率的设计结构
公开(公告)号：US20090113192A1
公开(公告)日：2009-04-30
申请号：US12132517
申请日：2008-06-03
申请人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
发明人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/3814 , G06F9/3851
摘要： A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器的指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

33. 发明申请

US20090063819A1 Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US20090063819A1
公开(公告)日：2009-03-05
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

34. 发明申请

US20080065855A1 DMAC Address Translation Miss Handling Mechanism 审中-公开
标题翻译： DMAC地址翻译小姐处理机制
公开(公告)号：US20080065855A1
公开(公告)日：2008-03-13
申请号：US11531293
申请日：2006-09-13
申请人： Matthew E. King , Peichun P. Liu , David Mui , Mydung N. Pham , Jieming Qi , Thuong Q. Truong
发明人： Matthew E. King , Peichun P. Liu , David Mui , Mydung N. Pham , Jieming Qi , Thuong Q. Truong
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/1045 , G06F12/1081 , G06F12/145
摘要： A memory management unit (MMU) performs address translation and protection using a segment table and page table model. Each DMA queue entry may include a MMU-miss dependency flag. The DMA issue mechanism uses the MMU-miss dependency flag to block the issue of commands that are known to result in a translation miss. However, the direct memory access engine does not block subsequent DMA commands from being issued until they receive a translation miss. When the MMU completes processing of a miss, the MMU sends a miss clear signal to the DMA control unit to reset all MMU-miss dependency flags. When the MMU sends a miss clear signal, the DMA control unit will reset all DMA queue entries with MMU-miss dependency flags set. DMA commands in the DMA queue that were blocked from issue by the MMU-miss dependency flag may now be selected by the DMA control unit for issue.
摘要翻译：存储器管理单元（MMU）使用段表和页表模型执行地址转换和保护。每个DMA队列条目可以包括MMU-miss依赖标志。 DMA问题机制使用MMU-miss依赖标志来阻止已知导致翻译缺失的命令的问题。然而，直接存储器访问引擎不会阻止随后的DMA命令被发出，直到它们接收到转换未命中。当MMU完成未命中的处理时，MMU向DMA控制单元发送未命中清除信号，以复位所有MMU-miss依赖标志。当MMU发送未命中清除信号时，DMA控制单元将重置所有设置了MMU-miss依赖标志的DMA队列条目。 DMA控制单元现在可以由DMA控制单元选择DMA队列中的DMA命令，由MMU-miss依赖标志阻止发布。

35. 发明申请

US20070295455A1 METHOD AND APPARATUS FOR ETCHING MATERIAL LAYERS WITH HIGH UNIFORMITY OF A LATERAL ETCH RATE ACROSS A SUBSTRATE 审中-公开
标题翻译：用于蚀刻材料层的方法和装置，其具有基于基板的侧向蚀刻速率的高均匀性
公开(公告)号：US20070295455A1
公开(公告)日：2007-12-27
申请号：US11831357
申请日：2007-07-31
申请人： David Mui , Wei Liu
发明人： David Mui , Wei Liu
IPC分类号： H01L21/3065
CPC分类号： H01L21/32137
摘要： A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.
摘要翻译：一种用于使用包括钝化气体的气体混合物在衬底上蚀刻具有高均匀度横向蚀刻速率的材料层的方法和装置。钝化气体被提供到衬底的周边区域以钝化被蚀刻的结构的侧壁。

36. 发明申请

US20070083680A1 System and method for improved DMAC translation mechanism 有权
标题翻译：改进DMAC翻译机制的系统和方法
公开(公告)号：US20070083680A1
公开(公告)日：2007-04-12
申请号：US11246585
申请日：2005-10-07
申请人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
发明人： Matthew Edward King , Peichun Peter Lui , David Mui , Jieming Qi
IPC分类号： G06F13/28
CPC分类号： G06F12/1081 , G06F13/28
摘要： A system and method for improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.
摘要翻译：提出了一种用于改进DMAC转换机制的系统和方法。 DMA命令根据DMA命令的传输大小和计算机系统一次传输的数据量“展开”。对于第一个DMA请求，DMA队列请求内存管理单元执行地址转换。 DMA队列从MMU接收实际页码，并且在随后的发布请求中，DMA队列向总线接口单元提供实际页号，而不访问MMU，直到传输跨进下一页。在每个DMA请求之后，滚动逻辑会递减DMA命令的传输大小，确定是否已经达到新的页面，确定DMA命令是否完成，并将后续的DMA请求的回写信息发送到DMA队列。

37. 发明申请

US20060026308A1 DMAC issue mechanism via streaming ID method 审中-公开
标题翻译： DMAC发行机制通过流ID方式
公开(公告)号：US20060026308A1
公开(公告)日：2006-02-02
申请号：US10902473
申请日：2004-07-29
申请人： Matthew King , Peichun Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichun Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/3625
摘要： An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/O) devices, and processor to external or system memory. Commands are then assigned to a slot based on the type of DMA command: load or store. Once assigned, the commands can be executed by alternating between the slots and by utilizing round robin systems within the slots in order to provide a more efficient manner to execute DMA commands.
摘要翻译：提供了用于执行直接存储器访问（DMA）命令的装置，方法和计算机程序。基于命令类型的软件将物理队列分为多个虚拟队列，例如处理器到处理器，处理器到输入/输出（I / O）设备，以及处理器到外部或系统存储器。然后根据DMA命令的类型将命令分配给一个插槽：加载或存储。一旦分配了这些命令，可以通过在时隙之间交替并且通过利用时隙内的循环系统来执行命令，以便提供更有效的方式来执行DMA命令。

38. 发明申请

US20050085090A1 Method for controlling accuracy and repeatability of an etch process 失效
标题翻译：用于控制蚀刻工艺的精度和重复性的方法
公开(公告)号：US20050085090A1
公开(公告)日：2005-04-21
申请号：US10690318
申请日：2003-10-21
申请人： David Mui , Wei Liu , Hiroki Sasano
发明人： David Mui , Wei Liu , Hiroki Sasano
IPC分类号： H01L21/3065 , G03F7/20 , H01L21/00 , H01L21/02 , H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/461
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.
摘要翻译：本发明的实施例通常涉及在处理平台（例如，集群工具）中蚀刻的方法，其中可以原位获得鲁棒的预蚀刻和蚀刻后数据。该方法包括以下步骤：获得衬底上特征的预蚀刻临界尺寸（CD）测量值，蚀刻该特征; 处理蚀刻的衬底以在蚀刻期间减少和/或去除沉积在特征上的侧壁聚合物，并获得后蚀刻的CD测量。可以使用CD测量来调整蚀刻工艺以提高器件制造的精度和可重复性。

39. 发明申请

US20050064719A1 Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition 失效
标题翻译：通过选择性侧壁聚合物沉积控制光刻胶修整工艺的临界尺寸微载荷的方法
公开(公告)号：US20050064719A1
公开(公告)日：2005-03-24
申请号：US10665934
申请日：2003-09-19
申请人： Wei Liu , David Mui
发明人： Wei Liu , David Mui
IPC分类号： H01L21/3065 , G03F7/40 , H01L21/027 , H01L21/311 , H01L21/302 , H01L21/00 , H01L21/461
CPC分类号： H01L21/31138 , G03F7/40 , H01L21/0274
摘要： A method for trimming photoresist features on a semiconductor substrate in a processing system. The method utilizes a process gas mixture comprising a hydrocarbon gas, an oxygen gas and an inert gas. The critical dimension (CD) microloading of the dense and the isolated regions can be eliminated and the photoresist trimming rate can also be reduced to enable better critical dimension (CD) control.
摘要翻译：一种用于在处理系统中修整半导体衬底上的光致抗蚀剂特征的方法。该方法利用包括烃气体，氧气和惰性气体的工艺气体混合物。可以消除致密和孤立区域的临界尺寸（CD）微载荷，并且还可以减少光刻胶修整速率，以实现更好的临界尺寸（CD）控制。

40. 发明申请

US20050027902A1 DMA completion mechanism 失效
标题翻译： DMA完成机制
公开(公告)号：US20050027902A1
公开(公告)日：2005-02-03
申请号：US10631541
申请日：2003-07-31
申请人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的方法，装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

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