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1. 发明申请

US20050027902A1 DMA completion mechanism 失效
标题翻译： DMA完成机制
公开(公告)号：US20050027902A1
公开(公告)日：2005-02-03
申请号：US10631541
申请日：2003-07-31
申请人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的方法，装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

2. 发明申请

US20070174508A1 NON-FENCED LIST DMA COMMAND MECHANISM 失效
标题翻译：非执行列表DMA命令机制
公开(公告)号：US20070174508A1
公开(公告)日：2007-07-26
申请号：US11686083
申请日：2007-03-14
申请人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ. Each list element comprises a stall bit indicating whether the list element is fenced and a DMA completion logic (DCL) is coupled to the at least one processor, the issue logic, and the RIL, and configured to indicate completion of all outstanding bus requests relating to the list element.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的DMA控制器（DMAC）。计算机系统具有至少一个处理器和系统存储器，该列表DMA命令涉及系统存储器的有效地址（EA），并且该至少一个处理器具有本地存储器。 DMAC包括耦合到本地存储器的DMA命令队列（DMAQ），并配置为从本地存储器接收列表DMA命令并使列表DMA命令入队。问题逻辑被耦合到DMAQ并被配置为向DMAQ发出问题请求。请求接口逻辑（RIL）耦合到DMAQ并被配置为基于发出请求读取列表DMA命令。 RIL还耦合到本地存储器并且被配置为向本地存储器发送提取请求以发起从本地存储器向DMAQ获取列表DMA命令的列表元素。每个列表元素包括停止比特，指示该列表元素是否被围栏，并且一个DMA完成逻辑（DCL）被耦合到该至少一个处理器，该发行逻辑和该RIL，并被配置为指示所有未完成的总线请求的完成到列表元素。

3. 发明申请

US20050027903A1 Non-fenced list DMA command mechanism 有权
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US20050027903A1
公开(公告)日：2005-02-03
申请号：US10631542
申请日：2003-07-31
申请人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichum Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的方法和装置。列表DMA命令涉及系统存储器的有效地址（EA）。系统中至少有一个处理器具有本地存储。列表DMA命令在DMA队列（DMAQ）中排队。列表元素从本地存储器获取到DMAQ。从DMAQ读取列表DMA命令。为列表元素发出总线请求。如果总线请求是最后一个请求，则确定当前列表元素是否是最后一个列表元素。如果当前列表元素不是最后的列表元素，则确定当前列表元素是否被围栏。如果当前列表元素没有围栏，则无论所有未完成的请求是否完成，都会获取下一个列表元素。

4. 发明申请

US20060026308A1 DMAC issue mechanism via streaming ID method 审中-公开
标题翻译： DMAC发行机制通过流ID方式
公开(公告)号：US20060026308A1
公开(公告)日：2006-02-02
申请号：US10902473
申请日：2004-07-29
申请人： Matthew King , Peichun Liu , David Mui , Takeshi Yamazaki
发明人： Matthew King , Peichun Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/3625
摘要： An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/O) devices, and processor to external or system memory. Commands are then assigned to a slot based on the type of DMA command: load or store. Once assigned, the commands can be executed by alternating between the slots and by utilizing round robin systems within the slots in order to provide a more efficient manner to execute DMA commands.
摘要翻译：提供了用于执行直接存储器访问（DMA）命令的装置，方法和计算机程序。基于命令类型的软件将物理队列分为多个虚拟队列，例如处理器到处理器，处理器到输入/输出（I / O）设备，以及处理器到外部或系统存储器。然后根据DMA命令的类型将命令分配给一个插槽：加载或存储。一旦分配了这些命令，可以通过在时隙之间交替并且通过利用时隙内的循环系统来执行命令，以便提供更有效的方式来执行DMA命令。

5. 发明申请

US20070174509A1 SYSTEM FOR ASYNCHRONOUS DMA COMMAND COMPLETION NOTIFICATION 失效
标题翻译：异步DMA命令完成通知系统
公开(公告)号：US20070174509A1
公开(公告)日：2007-07-26
申请号：US11695436
申请日：2007-04-02
申请人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.
摘要翻译：本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

6. 发明授权

US07203811B2 Non-fenced list DMA command mechanism 有权
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US07203811B2
公开(公告)日：2007-04-10
申请号：US10631542
申请日：2003-07-31
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G00F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a DMA queue (DMAQ). A list element is fetched from the local storage to the DMAQ. The list DMA command is read from the DMAQ. A bus request is issued for the list element. If the bus request is a last request, it is determined whether a current list element is a last list element. If the current list element is not the last list element, it is determined whether the current list element is fenced. If the current list element is not fenced, a next list element is fetched regardless of whether all outstanding requests are completed.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的方法和装置。列表DMA命令涉及系统存储器的有效地址（EA）。系统中至少有一个处理器具有本地存储。列表DMA命令在DMA队列（DMAQ）中排队。列表元素从本地存储器获取到DMAQ。从DMAQ读取列表DMA命令。为列表元素发出总线请求。如果总线请求是最后一个请求，则确定当前列表元素是否是最后一个列表元素。如果当前列表元素不是最后的列表元素，则确定当前列表元素是否被围栏。如果当前列表元素没有围栏，则无论所有未完成的请求是否完成，都会获取下一个列表元素。

7. 发明授权

US07512722B2 Method for completing a plurality of chained list DMA commands that include a fenced list DMA command element 失效
标题翻译：用于完成包括围栏列表DMA命令元素的多个链表DMA命令的方法
公开(公告)号：US07512722B2
公开(公告)日：2009-03-31
申请号：US10631541
申请日：2003-07-31
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28 , G06F9/46
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的方法，装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

8. 发明授权

US07877523B2 Apparatus, computer program product, and system for completing a plurality of chained list DMA commands that include a fenced list DMA command element 有权
标题翻译：装置，计算机程序产品和用于完成包括围栏列表DMA命令元素的多个链表DMA命令的系统
公开(公告)号：US07877523B2
公开(公告)日：2011-01-25
申请号：US12331733
申请日：2008-12-10
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/28
摘要： An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

9. 发明申请

US20090094388A1 DMA Completion Mechanism 有权
标题翻译： DMA完成机制
公开(公告)号：US20090094388A1
公开(公告)日：2009-04-09
申请号：US12331733
申请日：2008-12-10
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.
摘要翻译：提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的装置和计算机程序产品。确定DMA命令是否作为列表DMA命令链接在一起。在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

10. 发明授权

US07444435B2 Non-fenced list DMA command mechanism 失效
标题翻译：非围栏列表DMA命令机制
公开(公告)号：US07444435B2
公开(公告)日：2008-10-28
申请号：US11686083
申请日：2007-03-14
申请人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
发明人： Matthew Edward King , Peichum Peter Liu , David Mui , Takeshi Yamazaki
IPC分类号： G06F3/00 , G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one processor has a local storage. The DMAC includes a DMA command queue (DMAQ) coupled to the local storage and configured to receive the list DMA command from the local storage and to enqueue the list DMA command. An issue logic is coupled to the DMAQ and configured to issue an issue request to the DMAQ. A request interface logic (RIL) is coupled to the DMAQ and configured to read the list DMA command based on the issue request. The RIL is further coupled to the local storage and configured to send a fetch request to the local storage to initiate a fetch of a list element of the list DMA command from the local storage to the DMAQ. Each list element comprises a stall bit indicating whether the list element is fenced and a DMA completion logic (DCL) is coupled to the at least one processor, the issue logic, and the RIL, and configured to indicate completion of all outstanding bus requests relating to the list element.
摘要翻译：提供了一种用于处理计算机系统中的列表DMA命令的DMA控制器（DMAC）。计算机系统具有至少一个处理器和系统存储器，该列表DMA命令涉及系统存储器的有效地址（EA），并且该至少一个处理器具有本地存储器。 DMAC包括耦合到本地存储器的DMA命令队列（DMAQ），并配置为从本地存储器接收列表DMA命令并使列表DMA命令入队。问题逻辑被耦合到DMAQ并被配置为向DMAQ发出问题请求。请求接口逻辑（RIL）耦合到DMAQ并被配置为基于发出请求读取列表DMA命令。 RIL还耦合到本地存储器并且被配置为向本地存储器发送提取请求以发起从本地存储器向DMAQ获取列表DMA命令的列表元素。每个列表元素包括停止比特，指示该列表元素是否被围栏，并且一个DMA完成逻辑（DCL）被耦合到该至少一个处理器，该发行逻辑和该RIL，并被配置为指示所有未完成的总线请求的完成到列表元素。

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