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31. 发明申请

US20090245445A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：US20090245445A1
公开(公告)日：2009-10-01
申请号：US12370338
申请日：2009-02-12
申请人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
发明人： Makoto Saen , Kenichi Osada , Shigenobu Komatsu , Itaru Nonomura , Yasuhisa Shimazaki
IPC分类号： H04L7/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2924/14 , H01L2924/15311 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.
摘要翻译：一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

32. 发明申请

US20090157252A1 VEHICLE ELECTRONIC SYSTEM AND VEHICLE 失效
标题翻译：车辆电子系统和车辆
公开(公告)号：US20090157252A1
公开(公告)日：2009-06-18
申请号：US12335984
申请日：2008-12-16
申请人： Makoto Saen , Kenichi Osada , Shigeru Oho
发明人： Makoto Saen , Kenichi Osada , Shigeru Oho
IPC分类号： G06F7/00
CPC分类号： G07C5/0816
摘要： In a vehicle electronic system including a plurality of LSI boards, LSIS which cannot control a user interface such as image or audio directly issue a command for notifying a vehicle occupant of its own information via networks and an information control LSI receives the request to output a message. A mechanism for setting priority of processings regarding LSI status information notification to be lower than that of an apparatus control processing is provided in each of LSIs and networks so that real-time property of the apparatus control processing is maintained. In order to reduce network load regarding the LSI status information notification, a message content itself is stored in a memory in a vehicle information processing unit previously so that only an ID for identifying the message content is transmitted.
摘要翻译：在包括多个LSI板的车载电子系统中，无法控制诸如图像或音频的用户界面的LSIS直接发出用于通过网络通知车辆乘客自己的信息的命令，并且信息控制LSI接收输出信息。在LSI和网络的每一个中设置有用于将关于LSI状态信息通知的处理的优先级设置为低于设备控制处理的优先级的机制，从而保持设备控制处理的实时性。为了减少关于LSI状态信息通知的网络负载，消息内容本身预先存储在车辆信息处理单元中的存储器中，从而仅发送用于识别消息内容的ID。

33. 发明授权

US07954023B2 Semiconductor integrated circuit including power domains 有权
标题翻译：半导体集成电路包括电源域
公开(公告)号：US07954023B2
公开(公告)日：2011-05-31
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： G01R31/28
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

34. 发明申请

US20090160544A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20090160544A1
公开(公告)日：2009-06-25
申请号：US12342015
申请日：2008-12-22
申请人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
发明人： Kazuo Otsuga , Kenichi Osada , Yusuke Kanno
IPC分类号： H01L25/00
CPC分类号： H03K19/0016
摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.
摘要翻译：提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN）电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

35. 发明授权

US09286968B2 Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权
标题翻译：包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层
公开(公告)号：US09286968B2
公开(公告)日：2016-03-15
申请号：US13616435
申请日：2012-09-14
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致微图案化困难。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

36. 发明授权

US08633684B2 Detection system, semiconductor device, and data processing device 失效
标题翻译：检测系统，半导体器件和数据处理器件
公开(公告)号：US08633684B2
公开(公告)日：2014-01-21
申请号：US12917523
申请日：2010-11-02
申请人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译：为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式，电流实际上没有减少，发出报警信号。

37. 发明授权

US08531872B2 Semiconductor integrated circuit and manufacturing method thereof 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US08531872B2
公开(公告)日：2013-09-10
申请号：US13350340
申请日：2012-01-13
申请人： Masanao Yamaoka , Kenichi Osada , Shigenobu Komatsu
发明人： Masanao Yamaoka , Kenichi Osada , Shigenobu Komatsu
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译：实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。首先测量SRAM的PMOS和NMOS晶体管的阈值电压。控制信息根据确定结果被编程到控制存储器中。基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

38. 发明授权

US08451050B2 Information technology equipment 有权
标题翻译：信息技术设备
公开(公告)号：US08451050B2
公开(公告)日：2013-05-28
申请号：US12987112
申请日：2011-01-08
申请人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译：信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。

39. 发明授权

US08270230B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08270230B2
公开(公告)日：2012-09-18
申请号：US13353949
申请日：2012-01-19
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
IPC分类号： G11C11/00 , G11C7/10 , G11C5/14
CPC分类号： G11C8/08 , G11C11/412
摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
摘要翻译：半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动，。通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

40. 发明授权

US08264870B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08264870B2
公开(公告)日：2012-09-11
申请号：US12891208
申请日：2010-09-27
申请人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
发明人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译：当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗同时存储数据增加。因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

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