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1. 发明专利

AU5025072A CONTINUOUSLY CAST GRAIN ORIENTED STEEL SHEET 未知
公开(公告)号：AU5025072A
公开(公告)日：1974-06-20
申请号：AU5025072
申请日：1972-12-19
申请人： TATSUO OHYA , EIZO SAKUMA , MINORU MOTOYOSHI , MASAFUMI OKAMOTO , KIYOSHI TANAKA
发明人： OHYA TATSUO , SAKUMA EIZO , MOTOYOSHI MINORU , OKAMOTO MASAFUMI , TANAKA KIYOSHI
IPC分类号： C21D7/02 , C21D7/13 , C21D8/12 , C21D9/46 , C22C38/02

2. 发明申请

US20110221516A1 INFORMATION TECHNOLOGY EQUIPMENT 有权
标题翻译：信息技术设备
公开(公告)号：US20110221516A1
公开(公告)日：2011-09-15
申请号：US12987112
申请日：2011-01-08
申请人： Masanao YAMAOKA , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao YAMAOKA , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译：信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。

3. 发明申请

US20110115474A1 DETECTION SYSTEM, SEMICONDUCTOR DEVICE, AND DATA PROCESSING DEVICE 失效
标题翻译：检测系统，半导体器件和数据处理器件
公开(公告)号：US20110115474A1
公开(公告)日：2011-05-19
申请号：US12917523
申请日：2010-11-02
申请人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译：为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式，电流实际上没有减少，发出报警信号。

4. 发明申请

US20090079488A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090079488A1
公开(公告)日：2009-03-26
申请号：US12167233
申请日：2008-07-02
申请人： Minoru MOTOYOSHI , Yasuhiro Fujimura , Shigeru Nakahara
发明人： Minoru MOTOYOSHI , Yasuhiro Fujimura , Shigeru Nakahara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译：可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数第二主时钟线位于。

5. 发明授权

US08633684B2 Detection system, semiconductor device, and data processing device 失效
标题翻译：检测系统，半导体器件和数据处理器件
公开(公告)号：US08633684B2
公开(公告)日：2014-01-21
申请号：US12917523
申请日：2010-11-02
申请人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译：为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式，电流实际上没有减少，发出报警信号。

6. 发明授权

US08451050B2 Information technology equipment 有权
标题翻译：信息技术设备
公开(公告)号：US08451050B2
公开(公告)日：2013-05-28
申请号：US12987112
申请日：2011-01-08
申请人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
发明人： Masanao Yamaoka , Kenichi Osada , Minoru Motoyoshi , Tetsuya Fukuoka
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译：信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。

7. 发明授权

US07612599B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07612599B2
公开(公告)日：2009-11-03
申请号：US12167233
申请日：2008-07-02
申请人： Minoru Motoyoshi , Yasuhiro Fujimura , Shigeru Nakahara
发明人： Minoru Motoyoshi , Yasuhiro Fujimura , Shigeru Nakahara
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.
摘要翻译：可以通过抑制最终级时钟缓冲器和用于提供时钟的时钟分配电路之间的布线引线的波动来减小时钟偏移。考虑到实现时钟偏移的这种减少，时钟分配电路的上游形成为H树结构，并且最终级形成在局部鱼骨结构中。连接到最后级缓冲器的多个主时钟线包括第一主时钟线和第二主时钟线。用于从第一主时钟线接收时钟的多个第一触发器所在的单元布置允许行的数量不同于用于从第一主时钟线接收时钟的多个第一触发器的单元布置允许行数第二主时钟线位于。

8. 发明申请

US20090072877A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20090072877A1
公开(公告)日：2009-03-19
申请号：US12167236
申请日：2008-07-02
申请人： Tetsuya FUKUOKA , Shigeru Nakahara , Minoru Motoyoshi
发明人： Tetsuya FUKUOKA , Shigeru Nakahara , Minoru Motoyoshi
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.
摘要翻译：半导体集成电路包括第一从属时钟树802和第二从属时钟树803，其中，时钟被可变延迟电路805延迟并输入到第二从属时钟树803，使得相位彼此匹配输出来自终端时钟驱动器的时钟在相应树中具有相同的位置，从而减少时钟偏移。

9. 发明授权

US4006044A Steel slab containing silicon for use in electrical sheet and strip manufactured by continuous casting and method for manufacturing thereof 失效
标题翻译：含有硅的钢板，用于通过连续铸造制造的电工板和带材及其制造方法
公开(公告)号：US4006044A
公开(公告)日：1977-02-01
申请号：US563980
申请日：1975-04-01
申请人： Tatsuo Oya , Minoru Motoyoshi , Masfumi Okamoto , Kiyoshi Tanaka , Takayasu Sugiyama
发明人： Tatsuo Oya , Minoru Motoyoshi , Masfumi Okamoto , Kiyoshi Tanaka , Takayasu Sugiyama
IPC分类号： C21D8/12 , C22C38/02 , C04B35/00
CPC分类号： C21D8/12 , C21D8/1205 , C22C38/02
摘要： A steel slab containing silicon for use as an electrical steel sheet and strip and having no blister occurrence in the final product manufactured by continuous casting, characterized in that said slab comprises 2.5 - 4.0 wt.% of silicon, less than 0.04% of aluminium, less than 3 ppm of hydrogen or less than 3 ppm of hydrogen together with less than 80 ppm of oxygen, and less than [Al(%) .times. 10.sup.3 + 50] ppm of nitrogen, with the remainder being essentially iron.
摘要翻译：一种含硅的钢板，用作电工钢板和钢带，并且在通过连续铸造制造的最终产品中没有发生起泡，其特征在于，所述板坯包含2.5-4.0重量％的硅，小于0.04的铝，小于3ppm的氢或小于3ppm的氢以及小于80ppm的氧，小于[Al（％）×103 + 50] ppm的氮，其余基本上是铁。

10. 发明授权

US07629827B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07629827B2
公开(公告)日：2009-12-08
申请号：US12167236
申请日：2008-07-02
申请人： Tetsuya Fukuoka , Shigeru Nakahara , Minoru Motoyoshi
发明人： Tetsuya Fukuoka , Shigeru Nakahara , Minoru Motoyoshi
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.
摘要翻译：半导体集成电路包括第一从属时钟树802和第二从属时钟树803，其中，时钟被可变延迟电路805延迟并输入到第二从属时钟树803，使得相位彼此匹配输出来自终端时钟驱动器的时钟在相应树中具有相同的位置，从而减少时钟偏移。

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