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31. 发明授权

US08536632B2 FinFET with reduced gate to fin overlay sensitivity 有权
公开(公告)号：US08536632B2
公开(公告)日：2013-09-17
申请号：US13396291
申请日：2012-02-14
申请人： Kangguo Cheng , Louis L. Hsu , Jack A. Mandelman , John Edward Sheets, II
发明人： Kangguo Cheng , Louis L. Hsu , Jack A. Mandelman , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

32. 发明授权

US07868374B2 Semitubular metal-oxide-semiconductor field effect transistor 有权
标题翻译：半金属氧化物半导体场效应晶体管
公开(公告)号：US07868374B2
公开(公告)日：2011-01-11
申请号：US12034899
申请日：2008-02-21
申请人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
发明人： Kangguo Cheng , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L29/788
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译：在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

33. 发明授权

US07572682B2 Semiconductor structure for fuse and anti-fuse applications 失效
标题翻译：保险丝和反熔丝应用的半导体结构
公开(公告)号：US07572682B2
公开(公告)日：2009-08-11
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

34. 发明授权

US07381594B2 CMOS compatible shallow-trench efuse structure and method 失效
标题翻译： CMOS兼容浅沟槽结构和方法
公开(公告)号：US07381594B2
公开(公告)日：2008-06-03
申请号：US11290890
申请日：2005-11-30
申请人： Louis L. Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , Jack A. Mandelman , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/336 , H01L21/331
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译：提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

35. 发明授权

US06570207B2 Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex 失效
标题翻译：在使用垂直阵列器件单元复合体的DRAM工艺中创建垂直电容器和反熔丝的结构和方法
公开(公告)号：US06570207B2
公开(公告)日：2003-05-27
申请号：US09736496
申请日：2000-12-13
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L23/5252 , H01L27/10841 , H01L27/10864 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.
摘要翻译：提供一种集成电路芯片，其具有常规DRAM垂直传送装置和可以直接访问的集成垂直存储电容器或反熔丝，而不必打开传输门。直接访问集成电容器或反熔丝的机构可以是垂直单元内的修改的掺杂分布，其提供低电阻穿通FET。或者，机构可以是垂直单元内的一对重叠或几乎重叠的扩散。

36. 发明授权

US06538295B1 Salicide device with borderless contact 有权
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06538295B1
公开(公告)日：2003-03-25
申请号：US09645499
申请日：2000-08-25
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

37. 发明授权

US06524941B2 Sub-minimum wiring structure 失效
标题翻译：次最小布线结构
公开(公告)号：US06524941B2
公开(公告)日：2003-02-25
申请号：US09093910
申请日：1998-06-08
申请人： Louis L. Hsu , Jack A. Mandelman
发明人： Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/7682 , H01L21/76838 , H01L23/5256 , H01L23/5283 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.
摘要翻译：定位在多个导体之间的半导体布线结构，包括位于相邻导体上的间隔件和位于间隔件之间的至少一个布线元件。

38. 发明授权

US06335239B1 Manufacturing a DRAM cell having an annular signal transfer region 有权
标题翻译：制造具有环形信号传送区域的DRAM单元
公开(公告)号：US06335239B1
公开(公告)日：2002-01-01
申请号：US09641205
申请日：2000-08-18
申请人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
发明人： Farid Agahi , Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive connecting member couples the signal transfer region to a reference voltage to reduce floating body effects.
摘要翻译：一种存储器件，形成在具有形成在衬底中的侧壁的沟槽的衬底中。该器件包括位线导体和字线导体。信号存储节点具有形成在沟槽内的第一电极，第二电极和形成在第一和第二电极之间的节点电介质。信号传递装置具有：（i）环形信号传递区域，其外表面邻近沟槽的侧壁，内表面，第一端和第二端; （ii）将信号传送区域的第一端耦合到信号存储节点的第二电极的第一扩散区域; （iii）将信号传输区域的第二端耦合到位线导体的第二扩散区域; （iv）涂覆信号传送区域的内表面的栅极绝缘体; 和（v）涂覆栅极绝缘体并耦合到字线的栅极导体。导电连接构件将信号传递区域耦合到参考电压以减少浮体效应。

39. 发明授权

US06323086B2 Flash memory structure using sidewall floating gate having one side thereof surrounded by control gate 失效
标题翻译：使用侧壁浮动栅极的闪存结构，其一侧由控制栅极包围
公开(公告)号：US06323086B2
公开(公告)日：2001-11-27
申请号：US09298920
申请日：1998-06-15
申请人： Louis L. Hsu , Jack A. Mandelman
发明人： Louis L. Hsu , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115
摘要： A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall such that the spacer includes only one side which abuts the second sidewall of the polysilicon wordline.
摘要翻译：闪速存储器和形成闪速存储器的方法包括在衬底上形成多晶硅字线，所述字线具有第一和第二侧壁，所述第一侧壁相对于所述衬底的表面是渐缩的，以具有倾斜角和所述第二侧壁具有大于所述第一侧壁的倾斜角的倾斜角。此后，在第二侧壁上形成多晶硅间隔物，使得间隔物仅包括一个邻接多晶硅字线的第二侧壁的一侧。

40. 发明授权

US06174762B1 Salicide device with borderless contact 失效
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06174762B1
公开(公告)日：2001-01-16
申请号：US09260311
申请日：1999-03-02
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

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