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31. 发明申请

US20070040276A1 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US20070040276A1
公开(公告)日：2007-02-22
申请号：US11207218
申请日：2005-08-19
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

32. 发明申请

US20060234443A1 MIM capacitor and method of fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US20060234443A1
公开(公告)日：2006-10-19
申请号：US11106887
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。该方法包括与镶嵌互连线同时形成MIM电容器的部分。

33. 发明申请

US20050127511A1 Interconnect structures and methods of making thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US20050127511A1
公开(公告)日：2005-06-16
申请号：US10735845
申请日：2003-12-16
申请人： Chih-Chao Yang , Louis Hsu , Keith Wong , Timothy Dalton , Carl Radens , Larry Clevenger
发明人： Chih-Chao Yang , Louis Hsu , Keith Wong , Timothy Dalton , Carl Radens , Larry Clevenger
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76849 , H01L21/76862 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.
摘要翻译：制造互连结构的扩散阻挡层的方法。该方法包括：在底部电介质沟槽中提供导线; 在所述盖层上沉积牺牲衬垫; 沉积层间电介质; 在顶层间电介质中形成沟槽和通孔; 以及去除靠近通孔底表面的覆盖层和牺牲层的一部分。盖层和牺牲层的去除部分主要沿着通孔的下侧壁沉积。导线与盖层接触，牺牲层与盖层接触。本发明还涉及由本发明方法产生的互连结构。

34. 发明授权

US06777286B2 Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating 失效
$Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating$
标题翻译：含有难熔金属 - 硅 - 氮电阻元件的紧凑SRAM单元及其制造方法
公开(公告)号：US06777286B2
公开(公告)日：2004-08-17
申请号：US10616243
申请日：2003-07-08
申请人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
发明人： Lawrence Clevenger , Louis Hsu , Li-Kong Wang
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.
摘要翻译：描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

35. 发明申请

US20050180521A1 REDUNDANCY STRUCTURE AND METHOD FOR HIGH-SPEED SERIAL LINK 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US20050180521A1
公开(公告)日：2005-08-18
申请号：US10708240
申请日：2004-02-18
申请人： Louis Hsu , Carl Radens , Li-Kong Wang
发明人： Louis Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H04L1/22 , H04L25/02 , H04L25/08 , H04L27/04
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

36. 发明申请

US20060006166A1 On-chip power supply regulator and temperature control system 失效
标题翻译：片上电源调节器和温度控制系统
公开(公告)号：US20060006166A1
公开(公告)日：2006-01-12
申请号：US10884933
申请日：2004-07-06
申请人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
发明人： Howard Chen , William Ferrante , Louis Hsu , Carl Radens
IPC分类号： H05B1/02 , H05B3/00
CPC分类号： G05D23/20 , G05D23/1931 , Y10T307/469
摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.
摘要翻译：片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

37. 发明申请

US20050260801A1 High performance FET with elevated source/drain region 失效
标题翻译：具有升高的源极/漏极区域的高性能FET
公开(公告)号：US20050260801A1
公开(公告)日：2005-11-24
申请号：US10996866
申请日：2004-11-24
申请人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
发明人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
IPC分类号： H01L21/336 , H01L29/45 , H01L29/76 , H01L29/786
CPC分类号： H01L29/66553 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/7842 , H01L29/78618 , H01L29/78684
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

38. 发明申请

US20050112811A1 ULTRA-THIN SOI MOSFET METHOD AND STRUCTURE 失效
标题翻译：超薄SOI MOSFET方法和结构
公开(公告)号：US20050112811A1
公开(公告)日：2005-05-26
申请号：US10707200
申请日：2003-11-26
申请人： Louis Hsu , Carl Radens , Ramachandra Divakaruni
发明人： Louis Hsu , Carl Radens , Ramachandra Divakaruni
IPC分类号： H01L21/336 , H01L21/762 , H01L29/45 , H01L21/8234
CPC分类号： H01L29/66772 , H01L21/76283 , H01L29/458 , H01L29/66545
摘要： An ultra-thin, scaleable MOSFET transistor and fabrication method are described. The transistor features fully self-aligned, raised source/drain junctions on a thin SOI wafer and exhibits low contact resistance, low gate resistance and good device isolation characteristic. No extra lithographic mask steps are required beyond those required by conventional processes. The transistor is completely “bracketed” or surrounded by STI (shallow trench isolation), providing inherent isolation between it and any other devices on the SOI wafer. Gate sidewall spacers are formed outside of the gate area so that the scalability is limited solely by lithography resolution.
摘要翻译：描述了一种超薄的可扩展MOSFET晶体管和制造方法。晶体管在薄SOI晶圆上具有完全自对准的升高的源极/漏极结，并且具有低接触电阻，低栅极电阻和良好的器件隔离特性。不需要额外的光刻掩模步骤，超出传统工艺所需要的步骤。晶体管完全“包围”或被STI（浅沟槽隔离）包围，提供了SOI晶片上任何其他器件之间的固有隔离。栅极侧壁间隔物形成在栅极区域的外部，从而可扩展性仅由光刻分辨率限制。

39. 发明授权

US06524908B2 Method for forming refractory metal-silicon-nitrogen capacitors and structures formed 失效
$Method for forming refractory metal-silicon-nitrogen capacitors and structures formed$
标题翻译：形成难熔金属 - 硅 - 氮电容器和结构的方法
公开(公告)号：US06524908B2
公开(公告)日：2003-02-25
申请号：US09872603
申请日：2001-06-01
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
IPC分类号： H01L218242
CPC分类号： H01L28/75 , C23C14/0073 , C23C14/0641 , H01L21/2855 , H01L21/28568
摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.
摘要翻译：描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。在该方法中，首先将预处理的半导体衬底定位在溅射室中。然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

40. 发明申请

US20050227480A1 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US20050227480A1
公开(公告)日：2005-10-13
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/31 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

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