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    • 31. 发明授权
    • Semiconductor static memory device with cell grounding means for reduced
power consumption
    • 具有电池接地装置的半导体静态存储器件用于降低功耗
    • US4768166A
    • 1988-08-30
    • US97330
    • 1987-09-10
    • Kenji Anami
    • Kenji Anami
    • G11C11/41G11C8/12G11C8/14G11C11/417G11C11/418G11C11/419G11C7/00G11C8/00
    • G11C11/418G11C11/419G11C8/12G11C8/14
    • A semiconductor static memory device in which the power consumption is minimized. The memory cells are grouped in column blocks and rows. A NAND gate is provided for each such group, with the output of the NAND gate being coupled to the ground terminals of the cells in its group. The input terminals of the NAND gates receive respective row and column block selection signals. A potential generator is provided in each cell for boosting the potential of the ground terminal of the cell above the potential of the word line, less a threshold voltage of one of the access transistors of the cell, when the corresponding block is not selected. The NAND gates set the potential of the ground terminal at ground voltage when both the column block and word line signals applied thereto are in the high state.
    • 一种半导体静态存储器件,其功耗最小化。 存储单元被分组在列块和行中。 为每个这样的组提供了与非门,NAND门的输出耦合到其组中的单元的接地端。 NAND门的输入端子接收相应的行和列块选择信号。 在每个单元中提供电位发生器,用于当未选择相应的块时,将单元的电位以上的单元的接地端子的电位升高到单元的一个存取晶体管的阈值电压以下。 NAND门将施加于其上的列块和字线信号都处于高电平状态时,将接地端子的电位设置为接地电压。
    • 32. 发明授权
    • Integrated circuit operating as a current-mirror type CMOS amplifier
    • 集成电路作为电流镜式CMOS放大器工作
    • US4633192A
    • 1986-12-30
    • US607645
    • 1984-05-07
    • Kenji Anami
    • Kenji Anami
    • H03F3/45H01L21/8238H01L27/092H03F3/34H03F3/343H03F3/345H03F3/16
    • H03F3/345
    • An integrated circuit operates as a current-mirror type CMOS amplifier. The integrated circuit is constructed of a first inverter and a second inverter. The first inverter is formed of a first P-channel FET whose source is connected to a power supply with a gate and a drain thereof being connected to a first node; and a first N-channel FET whose drain is connected to the first node with a gate thereof being connected to a first input terminal and with a source thereof being earthed. The second inverter is formed of a second P-channel FET whose source is connected to a power supply with a gate thereof being connected to the first node and with a drain thereof being connected to a second node; and a second N-channel FET whose drain is connected to the second node with a gate thereof being connected to a second input terminal and with a source thereof being earthed. The first inverter and the second inverter having different conductances which vary according to a predetermined ratio in order to reduce current consumption.
    • 集成电路作为电流镜式CMOS放大器工作。 集成电路由第一反相器和第二反相器构成。 第一反相器由第一P沟道FET形成,其源极连接到电源,栅极和漏极连接到第一节点; 以及第一N沟道FET,其漏极连接到第一节点,其栅极连接到第一输入端子并且其源极接地。 第二反相器由第二P沟道FET形成,其源极连接到电源,其栅极连接到第一节点并且其漏极连接到第二节点; 以及第二N沟道FET,其漏极连接到第二节点,其栅极连接到第二输入端子并且其源极接地。 第一反相器和第二反相器具有根据预定比率变化的不同电导率,以便减少电流消耗。