专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06717871B2 Semiconductor device with flexible redundancy system 失效
公开(公告)号：US06717871B2
公开(公告)日：2004-04-06
申请号：US10310960
申请日：2002-12-06
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

32. 发明授权

US06567336B2 Semiconductor memory for logic-hybrid memory 有权
公开(公告)号：US06567336B2
公开(公告)日：2003-05-20
申请号：US09888649
申请日：2001-06-26
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C800
CPC分类号： G11C11/408 , G11C7/1078 , G11C7/22 , G11C8/00 , G11C8/20 , G11C2207/104
摘要： This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

33. 再颁专利

USRE37427E1 Dynamic type memory 有权
标题翻译：动态类型内存
公开(公告)号：USRE37427E1
公开(公告)日：2001-10-30
申请号：US09493001
申请日：2000-01-27
申请人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
发明人： Masaki Ogihara , Satoru Takase , Kiyofumi Sakurai
IPC分类号： G11C1300
CPC分类号： G11C7/1012 , G11C5/025 , G11C7/06 , G11C7/10 , G11C7/1006 , G11C11/4093 , G11C11/4096
摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.
摘要翻译：在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。每个子阵列设置有与字线并行形成的数据线。数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。这种布置允许数据路径被缩短并且能够高速传送数据。

34. 发明授权

US5642326A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5642326A
公开(公告)日：1997-06-24
申请号：US534558
申请日：1995-09-27
申请人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
发明人： Kiyofumi Sakurai , Satoru Takase , Masaki Ogihara
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/409 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C8/18
摘要： A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.
摘要翻译：动态存储器包括控制电路，用于根据外部提供给它的+ E，ovs RAS + EE信号和用于控制选定字线的字线控制电路来控制行解码器的选择和感测放大器的激活将连接到各个存储器单元的位线上连接到字线的存储单元读出的电位在由该位线对应的读出放大器在从+ E，ovs RAS + EE信号变为有效电平的时间段和其回到无效电平的时间。具有栅极氧化膜的动态存储器被设计为经受较少的电场强度以便最小化可靠性的劣化，并且存储器可以有效地减少字线驱动升压电压的下降以消除泄漏的必要性电流补偿电路。此外，存储器减少了恢复数据读取操作的电位所需的时间以及数据写入操作所需的周期时间。

35. 发明授权

US5341326A Semiconductor memory having memory cell units each including cascade-connected MOS transistors 失效
标题翻译：具有各自包括级联连接的MOS晶体管的存储单元单元的半导体存储器
公开(公告)号：US5341326A
公开(公告)日：1994-08-23
申请号：US833045
申请日：1992-02-10
申请人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
发明人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
IPC分类号： G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/108 , G11C11/24 , G11C11/34
CPC分类号： G11C11/565
摘要： A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.
摘要翻译：半导体存储单元包括级联栅极，其包括多个级联连接的MOS晶体管，并且其一端连接到第一节点;以及多个用于数据存储的电容器，其一端连接到MOS晶体管，分别在远离节点，并且存在关于电容器的电容的预定调节。

36. 发明授权

US08743587B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08743587B2
公开(公告)日：2014-06-03
申请号：US13197050
申请日：2011-08-03
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C13/0007 , G11C8/005 , G11C11/5685 , G11C13/0033 , G11C13/0069 , G11C14/00 , G11C16/3431 , G11C2211/5641
摘要： According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount.
摘要翻译：根据一个实施例，半导体存储器件包括第一单元，第一行，第二行，第一单元阵列和信号驱动器。第一个单元格处于第一状态或第二状态。处于第二状态的保持时间长于第一状态。第一个单元阵列具有在矩阵中形成的第一个单元。第一个单元通过第一个第二行电连接。信号驱动器驱动第一个单元。信号驱动器通过控制施加到第一单元的电压，电流和电荷量中的任何一个或这些的组合以及电压的波形来使第一单元转变到第一状态或第二状态，电流，电荷量和/或电压，电流和电荷量中的至少一个的传输时间长度。

37. 发明授权

US08040715B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08040715B2
公开(公告)日：2011-10-18
申请号：US12609617
申请日：2009-10-30
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C5/02 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0028 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72
摘要： Plural memory cell arrays laminated on the semiconductor substrate each includes a plurality of first wirings and second wirings formed to intersect with each other. The control circuit provides, in a non-selected second memory cell array that shares the first wiring with a selected first memory cell array, and a non-selected third memory cell array located more distant from the first memory cell array than the second memory cell array, the first potential to all of the first wirings and all of the second wirings. It also provides, in a non-selected fourth memory cell array that shares the second wiring with the first memory cell array and a non-selected fifth memory cell array located more distant from the first memory cell array than the fourth memory cell array, the second potential to all of the first wirings and all of the second wirings.
摘要翻译：层叠在半导体基板上的多个存储单元阵列各自包括形成为彼此交叉的多个第一布线和第二布线。控制电路在与所选择的第一存储单元阵列共享第一布线的未选择的第二存储单元阵列中提供位置比第二存储单元更远离第一存储单元阵列的未选择的第三存储单元阵列阵列，所有的第一个布线和所有第二个布线的第一个潜力。它还在与第一存储单元阵列共享第二布线的未选择的第四存储单元阵列和位于比第四存储单元阵列更远离第一存储单元阵列的未选择的第五存储单元阵列中，所有第一条布线和所有第二条布线的第二个潜力。

38. 发明申请

US20110103130A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20110103130A1
公开(公告)日：2011-05-05
申请号：US12987201
申请日：2011-01-10
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C11/00 , G11C8/08
CPC分类号： G11C13/0007 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.
摘要翻译：一种电阻变化存储装置，包括：具有设置在字线和位线的交叉点的存储单元的电阻变化型的单元阵列，可逆地设定存储单元的电阻值; 字线驱动器电路，被配置为向所述字线中选择的一个施加选择驱动电压; 以及位线驱动电路，其被配置为以这样的方式驱动多个位线，使得对于由所选择的字线选择的多个存储器单元同时设置设置模式和复位模式，所述设置模式用于将选择的存储器单元从第一电阻状态变为第二电阻状态，而复位模式用于将所选择的存储单元从第二电阻状态改变为第一电阻状态。

39. 发明授权

US07885121B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07885121B2
公开(公告)日：2011-02-08
申请号：US12245152
申请日：2008-10-03
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C16/06
CPC分类号： G11C13/0007 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.
摘要翻译：一种电阻变化存储装置，包括：具有设置在字线和位线的交叉点的存储单元的电阻变化型的单元阵列，可逆地设定存储单元的电阻值; 字线驱动器电路，被配置为向所述字线中选择的一个施加选择驱动电压; 以及位线驱动电路，其被配置为以这样的方式驱动多个位线，使得对于由所选择的字线选择的多个存储器单元同时设置设置模式和复位模式，所述设置模式用于将选择的存储器单元从第一电阻状态变为第二电阻状态，而复位模式用于将所选择的存储单元从第二电阻状态改变为第一电阻状态。

40. 发明授权

US07876626B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07876626B2
公开(公告)日：2011-01-25
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式