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31. 发明申请

US20050045966A1 Nonvolatile semiconductor memory and manufacturing method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法相同
公开(公告)号：US20050045966A1
公开(公告)日：2005-03-03
申请号：US10868773
申请日：2004-06-17
申请人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
发明人： Hiroki Yamashita , Yoshio Ozawa , Atsuhiro Sato
IPC分类号： H01L21/76 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/82 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L27/115 , H01L29/42324 , Y10T428/24256
摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
摘要翻译：半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层，在电极间电介质上。这里，器件隔离膜的上角被倒角。

32. 发明授权

US5822672A Copying machine 失效
标题翻译：复印机
公开(公告)号：US5822672A
公开(公告)日：1998-10-13
申请号：US711602
申请日：1996-09-10
申请人： Akiyoshi Johdai , Akira Ohhata , Hiroki Yamashita , Hirokazu Matsuo , Yoshihito Hirano
发明人： Akiyoshi Johdai , Akira Ohhata , Hiroki Yamashita , Hirokazu Matsuo , Yoshihito Hirano
IPC分类号： B65H5/02 , B65H7/20 , G03G15/00
CPC分类号： G03G15/60 , G03G2215/00185 , G03G2215/0032 , Y10S271/902
摘要： A copying machine having a two-in-one copying mode comprises a document feeder means 65, 75 and three conveying means 90, 95, 101. The feeder means 65, 75 feeds a document toward a glass platen 29 one by one to stop the document at a first-out position. The first conveying means 90 conveys the document fed by the feeder means 65, 75 onto the glass platen. The second conveying means 95 conveys the document conveyed by the first conveying means 90 along the glass platen 29 until the rear end of the document reaches at a predetermined switch-back position, then conveys the document to the opposite direction to retreat a predetermined distance, and then conveys the document as well as a succeeding document stopped at the first-out position such that the front end of the document situated on a downstream side of the document conveying direction may be aligned with a exposure reference SP, and then discharging the documents to the downstream side of the document conveying direction after exposure. The third conveying means 101 for conveying the documents discharged by the second conveying means 95 from the glass platen 29 to a discharge section 115.
摘要翻译：具有二合一复印模式的复印机包括文件馈送装置65,75和三个传送装置90,91,101。馈送装置65,75将文件一个接一个地朝向玻璃台板29送出，以停止以先到先得的位置记录。第一传送装置90将由馈送装置65,75馈送的文件传送到玻璃台板上。第二输送装置95沿着玻璃压板29输送由第一输送装置90输送的原稿，直到文件的后端到达预定的切换位置，然后将文件传送到相反的方向以退回预定的距离，然后传送原稿以及在首出位置停止的后续文件，使得位于文件传送方向的下游侧的文档的前端可以与曝光参考SP对准，然后排出文档到曝光后文件传送方向的下游侧。用于将由第二输送装置95排出的原稿从玻璃压板29输送到排出部115的第三输送装置101。

33. 发明授权

US4954866A Semiconductor integrated circuit memory 失效
标题翻译：半导体集成电路存储器
公开(公告)号：US4954866A
公开(公告)日：1990-09-04
申请号：US247250
申请日：1988-09-21
申请人： Hirotoshi Tanaka , Hiroki Yamashita , Noboru Masuda , Junji Shigeta , Yasunari Umemoto , Osamu Kagaya
发明人： Hirotoshi Tanaka , Hiroki Yamashita , Noboru Masuda , Junji Shigeta , Yasunari Umemoto , Osamu Kagaya
IPC分类号： H01L27/06 , H01L27/105 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0605 , H01L27/1116 , H01L27/105
摘要： A semiconductor integrated circuit memory is disclosed in which a first impurity-doped layer for making circuit elements such as MESFET's and a second impurity-doped layer opposite in conductivity type to the first impurity-doped layer are formed in a semi-insulating substrate in such a manner that the second impurity-doped layer is formed under and between circuit elements for making up a memory cell array part and a peripheral circuit part, and is divided into at least first and second regions. For example, the first region formed under and between the circuit elements of the memory cell array part is made of a P-type layer which is high in carrier density, and the second region formed under and between the circuit elements of the peripheral circuit part is made of a P-type layer which is low in carrier density. The high carrier-density P-type layer formed under the memory cell array part allows a memory cell having a minimum critical charge for alpha-particles to gain satisfactory alpha-particle immunity even when the memory cell is made fine in size. Further, the low carrier-density P-type layer formed under the peripheral circuit part having a critical charge larger than that of the memory cell can improve the alpha-particle immunity of the peripheral circuit part and can suppress an increase in parasitic capacitance at the peripheral circuit part to maintain the high-speed operation of the memory.
摘要翻译：公开了一种半导体集成电路存储器，其中在半绝缘衬底中形成用于制造电路元件的第一杂质掺杂层，例如MESFET和与第一杂质掺杂层的导电类型相反的第二杂质掺杂层第二杂质掺杂层形成在用于构成存储单元阵列部分的电路元件和外围电路部分之间的方式，并且被划分为至少第一和第二区域。例如，形成在存储单元阵列部分的电路元件之下和之间的第一区域由载流子密度高的P型层制成，并且第二区域形成在外围电路部分的电路元件之下由载流子浓度低的P型层构成。形成在存储单元阵列部分下方的高载流子密度P型层允许具有最小临界电荷的存储单元获得满意的α粒子免疫，即使当存储单元的尺寸精细时。此外，形成在具有大于存储单元的临界电荷的外围电路部分下的低载流子密度P型层可以改善外围电路部分的α粒子免疫力，并且可以抑制在外部电路部分的寄生电容的增加外围电路部分保持高速运行的内存。

34. 发明授权

US08445832B2 Optical communication device 有权
标题翻译：光通信设备
公开(公告)号：US08445832B2
公开(公告)日：2013-05-21
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/08 , H01J43/00 , H01J40/14 , G01R19/00
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

35. 发明授权

US08358708B2 Low offset input circuit and transmission system with the input circuit 有权
公开(公告)号：US08358708B2
公开(公告)日：2013-01-22
申请号：US12453980
申请日：2009-05-28
申请人： Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
发明人： Takashi Takemoto , Hiroki Yamashita , Masayoshi Yagyu
IPC分类号： H04L7/00
CPC分类号： H03F3/45475 , H03F3/24 , H03F3/3028 , H03F3/45183 , H03F3/45605 , H03F3/45977 , H03F2200/411 , H03F2200/537 , H03F2203/45212 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726
摘要： A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.

36. 发明授权

US08005130B2 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US08005130B2
公开(公告)日：2011-08-23
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

37. 发明授权

US07716747B2 Image processing apparatus, image processing method, computer program and computer-readable recording medium 有权
标题翻译：图像处理装置，图像处理方法，计算机程序和计算机可读记录介质
公开(公告)号：US07716747B2
公开(公告)日：2010-05-11
申请号：US10830180
申请日：2004-04-22
申请人： Satoru Wakao , Hiroki Yamashita
发明人： Satoru Wakao , Hiroki Yamashita
IPC分类号： G06F7/04 , G06F12/14
CPC分类号： H04N1/32128 , H04L9/3242 , H04L9/3247 , H04L2209/60 , H04N1/32112 , H04N2201/3233 , H04N2201/3242 , H04N2201/325
摘要： An image processing apparatus includes an alteration unit and a control unit. The alteration unit alters a first image file stored in a removable storage medium in order to generate a second image file. The control unit controls to store the second image file in the storage medium without deleting the first image file from the storage medium, if the first image file includes authentication data that is used to authenticate whether the first image file has been altered.
摘要翻译：图像处理装置包括改变单元和控制单元。改变单元改变存储在可移动存储介质中的第一图像文件，以便生成第二图像文件。如果第一图像文件包括用于认证第一图像文件是否被改变的认证数据，则控制单元控制将第二图像文件存储在存储介质中而不从存储介质中删除第一图像文件。

38. 发明授权

US07714644B2 Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US07714644B2
公开(公告)日：2010-05-11
申请号：US12166666
申请日：2008-07-02
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F1/26 , H03F1/34 , H03F3/45085 , H03F3/45183 , H03F3/45968 , H03F2200/372 , H03F2200/375 , H03F2203/45534
摘要： An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
摘要翻译：提供放大器电路块和补偿电路块。放大器电路块包括用于从输入信号中减去补偿电路块的输出信号的模拟加法器和在宽带中工作的放大器电路。补偿电路块包括在低频区域具有低失调电压和低噪声的放大器电路，用于从放大器电路的输出信号中减去放大器电路的输出信号并产生其差分信号的模拟加法器块以及用于将差分信号负反馈给模拟加法器的反馈电路块。放大器电路块可以通过差分信号的负反馈来减小偏移电压和低带噪声，同时整个放大器电路的工作频带可以由放大器电路的特性决定。

39. 发明申请

US20090194807A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090194807A1
公开(公告)日：2009-08-06
申请号：US11870839
申请日：2007-10-11
申请人： Wakako Takeuchi , Hiroshi Akahori , Hiroki Yamashita
发明人： Wakako Takeuchi , Hiroshi Akahori , Hiroki Yamashita
IPC分类号： H01L29/792 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A semiconductor memory device includes: a semiconductor substrate; an element isolation trench formed on the semiconductor substrate so as to surround an element region in which a memory element is to be formed; a first gate insulating film formed on the element region of the semiconductor substrate; a charge storing layer formed on the first gate insulating film; a second gate insulating film formed on the charge storing layer; a control electrode formed on the second gate insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor substrate along a channel direction of the charge storing layer; a sidewall oxide film formed on a side surface of the element isolation trench; and an element isolation insulating film formed so as to fill the element isolation trench together with the element isolation insulation film; wherein the top surface of the sidewall oxide film is flush with or above the top surface of the first gate insulating film.
摘要翻译：半导体存储器件包括：半导体衬底; 元件隔离沟槽，形成在所述半导体衬底上，以围绕要形成存储元件的元件区域; 形成在所述半导体基板的所述元件区域上的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上的电荷存储层; 形成在所述电荷存储层上的第二栅极绝缘膜; 形成在所述第二栅极绝缘膜上的控制电极; 形成在电荷存储层的沟道方向上的半导体衬底的表面层中的杂质扩散层; 形成在所述元件隔离沟槽的侧表面上的侧壁氧化膜; 以及形成为与元件隔离绝缘膜一起填充元件隔离沟槽的元件隔离绝缘膜; 其中所述侧壁氧化物膜的顶表面与所述第一栅极绝缘膜的顶表面齐平或高于所述第一栅极绝缘膜的顶表面。

40. 发明授权

US06913444B2 Thin-form centrifugal fan 有权
标题翻译：薄型离心风机
公开(公告)号：US06913444B2
公开(公告)日：2005-07-05
申请号：US10389104
申请日：2003-03-14
申请人： Hirofumi Kariya , Hiroki Yamashita
发明人： Hirofumi Kariya , Hiroki Yamashita
IPC分类号： F04D17/12 , F04D17/16 , F04D25/16 , F04D29/28 , F04D29/44 , F04D17/00
CPC分类号： F04D29/282 , F04D17/164
摘要： A small, lightweight and inexpensive thin-form centrifugal fan having a first moving blade; a second moving blade; and a stationary blade disposed between the first moving blade and the second moving blade and directing gas taken in by rotation of the first moving blade to the second moving blade. The first and second moving blades are formed such that the rigidity of their central portions is smaller than the rigidity of their outer perimeter areas.
摘要翻译：一种小型，重量轻且廉价的薄型离心式风扇，具有第一活动叶片; 第二动叶片; 以及固定刀片，其设置在所述第一动叶片和所述第二动叶片之间，并且引导通过所述第一动叶片旋转而被吸入所述第二动叶片的气体。第一和第二移动叶片形成为使得其中心部分的刚性小于其外周边区域的刚性。

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