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31. 发明申请

US20070187734A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 失效
标题翻译：具有增强电容的CMOS成像器光电二极管
公开(公告)号：US20070187734A1
公开(公告)日：2007-08-16
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

32. 发明申请

US20060102939A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 审中-公开
公开(公告)号：US20060102939A1
公开(公告)日：2006-05-18
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

33. 发明申请

US20070202635A1 MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME 有权
标题翻译：多导体半导体绝缘体（SOI）衬底及其制造方法
公开(公告)号：US20070202635A1
公开(公告)日：2007-08-30
申请号：US11276366
申请日：2006-02-27
申请人： John Ellis-Monaghan , Mark Jaffe
发明人： John Ellis-Monaghan , Mark Jaffe
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/76264 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045
摘要： The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.
摘要翻译：本发明涉及绝缘体上半导体（SOI）衬底结构，其包含直接位于绝缘体层上的不同晶体取向的表面半导体区域。本发明还涉及制造这种SOI衬底结构的方法，通过直接在多取向体半导体衬底上生长绝缘体层，该绝缘体层包括直接位于半导体基底层上的不同晶体取向的表面半导体区域，以及去除半导体基底从而形成包括直接位于绝缘体层上的不同晶体取向的表面半导体区域的多取向SOI衬底结构。

34. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

35. 发明申请

US20050101072A1 Transistor structure with thick recessed source/drain structures and fabrication process of same 失效
公开(公告)号：US20050101072A1
公开(公告)日：2005-05-12
申请号：US11007843
申请日：2004-12-09
申请人： Andres Bryant , Mark Jaffe
发明人： Andres Bryant , Mark Jaffe
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/00 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/42384 , H01L29/66772 , H01L29/66795
摘要： An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

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