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31. 发明授权

US06288422B1 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
标题翻译：用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺
公开(公告)号：US06288422B1
公开(公告)日：2001-09-11
申请号：US09540276
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.
摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

32. 发明授权

US06911384B2 Gate structure with independently tailored vertical doping profile 失效
标题翻译：门结构具有独立定制的垂直掺杂特性
公开(公告)号：US06911384B2
公开(公告)日：2005-06-28
申请号：US10605697
申请日：2003-10-21
申请人： Omer Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl Radens
发明人： Omer Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl Radens
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/49 , H01L21/3205
CPC分类号： H01L29/66545 , H01L21/26586 , H01L21/28035 , H01L21/28044 , H01L29/1083 , H01L29/4925 , H01L29/665
摘要： A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
摘要翻译：公开了一种用于半导体晶体管的栅极结构。在示例性实施例中，栅极结构包括以第一掺杂剂浓度掺杂的下多晶硅区域和以第二浓度掺杂的上多晶硅区域，其中第二浓度不同于第一浓度。导电阻挡层设置在下部和上部多晶硅区域之间，其中导电阻挡层防止杂质在下部和上部多晶硅区域之间的扩散。

33. 发明申请

US20090117360A1 SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT 审中-公开
标题翻译：自组装材料模式转移对比增强
公开(公告)号：US20090117360A1
公开(公告)日：2009-05-07
申请号：US11933760
申请日：2007-11-01
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Habib Hichri , Louis L. Hsu , Kaushik A. Kumar , Carl Radens , Shahab Siddiqui , Chih-Chao Yang
IPC分类号： G03C1/73 , B05D3/00 , B32B27/06
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y30/00 , H01L21/0338
摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.
摘要翻译：含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

34. 发明授权

US07115921B2 Nano-scaled gate structure with self-interconnect capabilities 失效
标题翻译：具有自相互连接能力的纳米级栅极结构
公开(公告)号：US07115921B2
公开(公告)日：2006-10-03
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/80 , H01L29/76 , H01L21/337 , H01L21/336
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.
摘要翻译：集成电路上的栅极导体形成有用于将栅极导体与其它器件电连接的较大的上部。半导体器件包括具有扩大上部的栅极导体，该栅极导体将栅极导体电连接到局部扩散区。另一个半导体器件包括两个栅极导体，其具有扩大的上部，其合并以产生电互连的栅极导体。还描述和要求保护形成上述半导体器件的方法。

35. 发明授权

US06556477B2 Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same 有权
标题翻译：具有SRAM，DRAM和闪速存储器的集成芯片及其制造方法
公开(公告)号：US06556477B2
公开(公告)日：2003-04-29
申请号：US09861788
申请日：2001-05-21
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
IPC分类号： G11C1134
CPC分类号： H01L27/105 , G11C11/005 , H01L27/1052
摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.
摘要翻译：提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。在一个实施例中，SRAM器件是高电阻负载SRAM器件。在另一个实施例中，DRAM器件是深沟槽DRAM器件。还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

36. 发明授权

US07447273B2 Redundancy structure and method for high-speed serial link 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US07447273B2
公开(公告)日：2008-11-04
申请号：US10708240
申请日：2004-02-18
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H01L21/82 , H01P1/10
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

37. 发明授权

US07365001B2 Interconnect structures and methods of making thereof 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07365001B2
公开(公告)日：2008-04-29
申请号：US10735845
申请日：2003-12-16
申请人： Chih-Chao Yang , Louis L. Hsu , Keith Kwong Hon Wong , Timothy Joseph Dalton , Carl Radens , Larry Clevenger
发明人： Chih-Chao Yang , Louis L. Hsu , Keith Kwong Hon Wong , Timothy Joseph Dalton , Carl Radens , Larry Clevenger
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76849 , H01L21/76862 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.
摘要翻译：制造互连结构的扩散阻挡层的方法。该方法包括：在底部电介质沟槽中提供导线; 在所述盖层上沉积牺牲衬垫; 沉积层间电介质; 在顶层间电介质中形成沟槽和通孔; 以及去除靠近通孔底表面的覆盖层和牺牲层的一部分。盖层和牺牲层的去除部分主要沿着通孔的下侧壁沉积。导线与盖层接触，牺牲层与盖层接触。本发明还涉及由本发明方法产生的互连结构。

38. 发明授权

US07092235B2 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US07092235B2
公开(公告)日：2006-08-15
申请号：US11043760
申请日：2005-01-26
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/06
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。多个导电层被一层电介质材料隔开。电容器的电介质材料暴露于离子束。离子束包括至少一种材料的离子，以改变介电材料的介电常数。

39. 发明授权

US06869895B1 Method for adjusting capacitance of an on-chip capacitor 失效
标题翻译：调整片上电容器电容的方法
公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/255 , H01L21/02 , H01L21/66 , H01L21/31
CPC分类号： H01G4/255 , H01L22/22 , H01L28/40
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译：用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。

40. 发明授权

US08304912B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US08304912B2
公开(公告)日：2012-11-06
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

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