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31. 发明授权

US6139702A Seasoning process for etcher 有权
标题翻译：蚀刻机调味过程
公开(公告)号：US6139702A
公开(公告)日：2000-10-31
申请号：US263386
申请日：1999-03-05
申请人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
IPC分类号： C23C14/06 , C23C14/34 , H01L21/311 , G23C14/34
CPC分类号： C23C14/0682 , C23C14/3457 , H01L21/31116
摘要： A seasoning process for an etcher which is performed before etching a dielectric layer to expose a metal silicide layer. The seasoning process includes the first plasma sputtering process and the second plasma sputtering process. A wafer containing the metal silicide layer thereon is placed in the etcher with an etchant and the first plasma sputtering process is performed. Several silicon wafers are successively placed in the etcher to perform the second plasma sputtering process.
摘要翻译：在蚀刻介电层以暴露金属硅化物层之前执行的蚀刻器的调味过程。调味过程包括第一等离子体溅射工艺和第二等离子体溅射工艺。将含有其上的金属硅化物层的晶片用蚀刻剂放置在蚀刻器中，并且执行第一等离子体溅射工艺。将几个硅晶片依次放置在蚀刻器中以进行第二等离子体溅射工艺。

32. 发明授权

US08946031B2 Method for fabricating MOS device 有权
标题翻译：制造MOS器件的方法
公开(公告)号：US08946031B2
公开(公告)日：2015-02-03
申请号：US13353227
申请日：2012-01-18
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66803
摘要： A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.
摘要翻译：描述制造MOS器件的方法。第一硬掩模层形成在衬底上。第一硬掩模层被图案化并且去除衬底的一部分以形成第一图案化硬掩模，以及由沟槽包围并沿第一方向延伸的鳍结构。在沟槽底部形成绝缘层。在绝缘层上形成栅极导电层，沿第二方向延伸。使用第一图案化硬掩模作为掩模来执行第一注入工艺，以在翅片结构的侧壁中形成第一S / D延伸区域。去除第一图案化硬掩模以暴露鳍结构的顶部，然后执行第二注入工艺以在其中形成第二S / D延伸区域。

33. 发明授权

US08871575B2 Method of fabricating field effect transistor with fin structure 有权
标题翻译：制造鳍片结构的场效应晶体管的方法
公开(公告)号：US08871575B2
公开(公告)日：2014-10-28
申请号：US13284987
申请日：2011-10-31
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/00 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7851 , H01L29/0649 , H01L29/66545 , H01L29/66818
摘要： A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise. The trench is disposed over portions of the fin structure, and a lengthwise direction of the trench intersects a lengthwise direction of the fin structure, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed.
摘要翻译：描述了制造具有翅片结构的场效应晶体管的方法。至少在基板上形成翅片结构。形成覆盖翅片结构的平面绝缘层。在绝缘层中形成沟槽，并且纵向地与鳍结构相交。沟槽设置在翅片结构的一部分上，并且沟槽的长度方向与翅片结构的长度方向相交，从而翅片结构的上部暴露于沟槽。鳍结构的暴露的上部将用作栅极沟道区。在沟槽内形成覆盖上部的栅极结构。翅片结构的上部可以进一步修整。

34. 发明授权

US08698199B2 FinFET structure 有权
标题翻译： FinFET结构
公开(公告)号：US08698199B2
公开(公告)日：2014-04-15
申请号：US13347707
申请日：2012-01-11
申请人： Tong-Yu Chen , Chih-Jung Wang
发明人： Tong-Yu Chen , Chih-Jung Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66787 , H01L29/7843
摘要： A finFET device includes a substrate, at least a first fin structure disposed on the substrate, a L-shaped insulator surrounding the first fin structure and exposing, at least partially, the sidewalls of the first fin structure, wherein the height of the L-shaped insulator is inferior to the height of the first fin structure in order to expose parts of the sidewalls surface of the first fin structure, and a gate structure disposed partially on the L-shaped insulator and partially on the first fin structure.
摘要翻译： finFET器件包括衬底，至少设置在衬底上的第一鳍结构，围绕第一鳍结构并且至少部分地暴露第一鳍结构的侧壁的L形绝缘体，其中，为了露出第一鳍片结构的侧壁表面的部分，以及部分地设置在L形绝缘体上并部分地设置在第一鳍片结构上的栅极结构，第一翅片结构的高度劣于第一翅片结构的高度。

35. 发明申请

US20130334588A1 FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20130334588A1
公开(公告)日：2013-12-19
申请号：US13517759
申请日：2012-06-14
申请人： Tong-Yu Chen , Chih-Jung Wang
发明人： Tong-Yu Chen , Chih-Jung Wang
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/66833 , H01L21/28282 , H01L21/31111 , H01L21/31144 , H01L29/42344 , H01L29/66795 , H01L29/785 , H01L29/792
摘要： A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

36. 发明申请

US20130183804A1 METHOD FOR FABRICATING MOS DEVICE 有权
标题翻译：制造MOS器件的方法
公开(公告)号：US20130183804A1
公开(公告)日：2013-07-18
申请号：US13353227
申请日：2012-01-18
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66803
摘要： A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.
摘要翻译：描述制造MOS器件的方法。第一硬掩模层形成在衬底上。第一硬掩模层被图案化并且去除衬底的一部分以形成第一图案化硬掩模，以及由沟槽包围并沿第一方向延伸的鳍结构。在沟槽底部形成绝缘层。在绝缘层上形成栅极导电层，沿第二方向延伸。使用第一图案化硬掩模作为掩模来执行第一注入工艺，以在翅片结构的侧壁中形成第一S / D延伸区域。去除第一图案化硬掩模以暴露鳍结构的顶部，然后执行第二注入工艺以在其中形成第二S / D延伸区域。

37. 发明授权

US06806182B2 Method for eliminating via resistance shift in organic ILD 失效
标题翻译：消除有机ILD中电阻移位的方法
公开(公告)号：US06806182B2
公开(公告)日：2004-10-19
申请号：US10137274
申请日：2002-05-01
申请人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
发明人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
IPC分类号： H01L214763
CPC分类号： H01L21/02252 , H01L21/02118 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02304 , H01L21/02323 , H01L21/0234 , H01L21/3121 , H01L21/31695 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
摘要翻译：在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

38. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

39. 发明授权

US06559004B1 Method for forming three dimensional semiconductor structure and three dimensional capacitor 有权
标题翻译：形成三维半导体结构和三维电容器的方法
公开(公告)号：US06559004B1
公开(公告)日：2003-05-06
申请号：US10011760
申请日：2001-12-11
申请人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
发明人： Gwo-Shii Yang , Hsueh-Chung Chen , Chiung-Sheng Hsiung , Tong-Yu Chen , Sung-Hsiung Wang
IPC分类号： H01L21336
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
摘要翻译：一种用于形成具有垂直电容器而不是水平电容器的三维半导体结构的方法。该方法基本上至少包括在电介质层内形成底板的这些步骤，在底板上形成另一电介质层，在底板上移除所有电介质层，在底板上形成可选的衬垫和电容器电介质层，以及形成顶板电容电介质层。注意，底板的形状与底部连接和垂直手指相同，还注意到底板中的每个间隙都由电容器介电层和顶板填充。

40. 发明授权

US06218084B1 Method for removing photoresist layer 有权
公开(公告)号：US06218084B1
公开(公告)日：2001-04-17
申请号：US09212727
申请日：1998-12-15
申请人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
IPC分类号： G03F742
CPC分类号： H01L21/31138 , G03F7/427 , H01L21/31116
摘要： A method described for removing a photoresist/polymers layer on a substrate. The method comprises the steps of providing a wafer having an oxide layer, a photoresist/polymers layer, an opening penetrating through the photoresist/polymers layer and the oxide layer, and the sidewall polymer on the surface of photoresist layer and the oxide layer. An in-situ plasma-etching step using an additional gas mixed with oxygen as source is performed to remove the photoresist/polymers layer without residues, no damages to substrate and oxide and no changes on the critical dimension of the opening during etching step.

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