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31. 发明授权

US07505296B2 Ternary content addressable memory with block encoding 失效
标题翻译：具有块编码的三元内容可寻址存储器
公开(公告)号：US07505296B2
公开(公告)日：2009-03-17
申请号：US11877310
申请日：2007-10-23
申请人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译：有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

32. 发明授权

US07397695B2 Semiconductor memory apparatus and method for writing in the memory 有权
标题翻译：用于在存储器中写入的半导体存储装置和方法
公开(公告)号：US07397695B2
公开(公告)日：2008-07-08
申请号：US11409097
申请日：2006-04-24
申请人： Kiyoshi Nakai , Kazuhiko Kajigaya
发明人： Kiyoshi Nakai , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0042 , G11C2013/0076 , G11C2213/79
摘要： A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This difference is amplified by a sense amplifier SA and read out. Immediately before latching cell data by the sense amplifier, an NMOS transistor MN1 is turned off to disconnect a memory cell part from a sense amplifier part. An NMOS transistor MN10 then is turned on so that data on the selected word line are all in the set state. If then writing is to be carried out, writing is carried out in the sense amplifier SA from signal lines LIO and RIO, which are I/O lines. However, writing is not performed in the memory cells. Before a precharge command is entered to precharge the word line WL0L, under, the NMOS transistor MN1 is again turned on to write reset in the cell MC0.
摘要翻译：与DRAM兼容性高的相变存储器。如果连接到字线WL 0 L的单元MC 0具有低电阻，则流过其的电流高于在虚设单元MR 0中流动的电流，因此位线SA_B处于比其低的电位的位线SA_T。该差异由读出放大器SA放大并读出。在由读出放大器锁存单元数据之前，NMOS晶体管MN 1被截止以将存储单元部分与读出放大器部分断开。然后，NMOS晶体管MN 10导通，使得所选择的字线上的数据都处于设置状态。如果要进行写入，则在来自作为I / O线的信号线LIO和RIO的读出放大器SA中进行写入。但是，在存储单元中不执行写入。在进行预充电指令以预充电字线WL 0 L之前，NMOS晶体管MN 1再次导通以在单元MC 0中写入复位。

33. 发明申请

US20080100337A1 Memory circuit, semiconductor device and read control method of memory circuit 有权
标题翻译：存储电路，半导体器件和存储电路的读取控制方法
公开(公告)号：US20080100337A1
公开(公告)日：2008-05-01
申请号：US11976853
申请日：2007-10-29
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting one of the N look-up tables by decoding a look-up table select signal and for selecting M memory cells to be accessed included in the selected look-up table by decoding an L-bit logic input signal of the logic function; and a select connect circuit for selectively connecting the input/output paths of the M memory cells to be accessed with an input/output bus for transmitting an M-bit logic output signal of the logic function in response to a decoded result of the decode circuit.
摘要翻译：本发明的存储器电路包括N个查找表，用于通过将包括多个存储器单元的存储单元阵列分成各自对应于至少预定数量的输入/输出的部分来实现L个输入/ M输出的所需逻辑功能路径解码电路，用于通过解码查找表选择信号并通过解码所选择的查找表中包括的M个要存储的M个存储单元来选择N个查找表中的一个，逻辑功能; 以及选择连接电路，用于响应于解码电路的解码结果选择性地将要访问的M个存储单元的输入/输出路径与用于发送逻辑功能的M位逻辑输出信号的输入/输出总线相连接。

34. 发明授权

US07307909B2 Self-refresh timer circuit and method of adjusting self-refresh timer period 有权
标题翻译：自刷新定时器电路及调整自刷新定时器周期的方法
公开(公告)号：US07307909B2
公开(公告)日：2007-12-11
申请号：US11297646
申请日：2005-12-09
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.
摘要翻译：一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

35. 发明申请

US20070070716A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070070716A1
公开(公告)日：2007-03-29
申请号：US11598702
申请日：2006-11-14
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译：实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。在写入驱动器中提供锁存器。通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活的预充电信号。由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

36. 发明申请

US20060211231A1 Memory device and manufacturing method thereof 失效
公开(公告)号：US20060211231A1
公开(公告)日：2006-09-21
申请号：US11374074
申请日：2006-03-14
申请人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
发明人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
IPC分类号： H01L21/3205
CPC分类号： G11C13/0004 , G11C11/005 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

37. 发明申请

US20060158924A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060158924A1
公开(公告)日：2006-07-20
申请号：US11280170
申请日：2005-11-17
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译：从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压晶体管经由存储单元晶体管写入电容器的存储节点。此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

38. 发明申请

US20060142988A1 Design methodology and manufacturing method for semiconductor memory 审中-公开
标题翻译：半导体存储器的设计方法和制造方法
公开(公告)号：US20060142988A1
公开(公告)日：2006-06-29
申请号：US11318431
申请日：2005-12-28
申请人： Satoru Akiyama , Tomonori Sekiguchi , Takayuki Kawahara , Kazuhiko Kajigaya
发明人： Satoru Akiyama , Tomonori Sekiguchi , Takayuki Kawahara , Kazuhiko Kajigaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10 , G06F2217/78
摘要： A manufacturing method for semiconductor memory and a semiconductor design device, which can facilitate design and reduce a period of time required for the design, are provided. For example, when a designed memory array is verified, a read-out signal of a memory cell formulated by functions of respective parameters having various distributions is used. A value of the read-out signal is calculated by using a value extracted randomly from the distribution for each kind of parameter. Quality of the memory cell is determined from a calculated result. Calculation of the value of the read-out signal and determination of the quality of the memory cell are carried out to a great number of memory cells the memory array has. The total number of failed bits and the like obtained from these is used as an evaluation criterion.
摘要翻译：提供一种半导体存储器和半导体设计装置的制造方法，其可以促进设计并减少设计所需的时间。例如，当设计的存储器阵列被验证时，使用由具有各种分布的各个参数的功能所制定的存储器单元的读出信号。通过使用从各种参数的分布中随机提取的值来计算读出信号的值。从计算结果确定存储单元的质量。对存储器阵列具有的大量存储单元执行读出信号的值的计算和存储单元的质量的确定。将从这些获得的故障比特等的总数用作评估标准。

39. 发明申请

US20060120125A1 Semiconductor memory device and defect remedying method thereof 失效
公开(公告)号：US20060120125A1
公开(公告)日：2006-06-08
申请号：US11330220
申请日：2006-01-12
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C19/08
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

40. 发明申请

US20060024875A1 Semiconductor integrated circuit device and process for manufacturing the same 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060024875A1
公开(公告)日：2006-02-02
申请号：US11234118
申请日：2005-09-26
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Kazuhiko Kajigaya , Hideo Aoki , Isamu Asano
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Kazuhiko Kajigaya , Hideo Aoki , Isamu Asano
IPC分类号： H01L21/8234
CPC分类号： H01L21/2652 , H01L21/32051 , H01L21/32053 , H01L21/324 , H01L21/76802 , H01L21/76849 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L21/823814 , H01L21/823871 , H01L23/53257 , H01L27/1052 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10882 , H01L27/10894 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.
摘要翻译：在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

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