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1. 发明申请

US20060145667A1 Self-refresh timer circuit and method of adjusting self-refresh timer period 有权
公开(公告)号：US20060145667A1
公开(公告)日：2006-07-06
申请号：US11297646
申请日：2005-12-09
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： H02J7/04
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

2. 发明授权

US07515496B2 Self-refresh timer circuit and method of adjusting self-refresh timer period 失效
标题翻译：自刷新定时器电路及调整自刷新定时器周期的方法
公开(公告)号：US07515496B2
公开(公告)日：2009-04-07
申请号：US11984352
申请日：2007-11-16
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.
摘要翻译：一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

3. 发明授权

US07307909B2 Self-refresh timer circuit and method of adjusting self-refresh timer period 有权
标题翻译：自刷新定时器电路及调整自刷新定时器周期的方法
公开(公告)号：US07307909B2
公开(公告)日：2007-12-11
申请号：US11297646
申请日：2005-12-09
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.
摘要翻译：一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

4. 发明申请

US20080074940A1 Self-refresh timer circuit and method of adjusting self-refresh timer period 失效
标题翻译：自刷新定时器电路及调整自刷新定时器周期的方法
公开(公告)号：US20080074940A1
公开(公告)日：2008-03-27
申请号：US11984352
申请日：2007-11-16
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： G11C7/04
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.
摘要翻译：一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

5. 发明授权

US07978543B2 Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same 有权
标题翻译：半导体器件可以测试多个存储单元的质量并行测试方法
公开(公告)号：US07978543B2
公开(公告)日：2011-07-12
申请号：US12488920
申请日：2009-06-22
申请人： Hideo Inaba , Tadashi Onodera
发明人： Hideo Inaba , Tadashi Onodera
IPC分类号： G11C7/10
CPC分类号： G11C29/48 , G11C29/1201
摘要： A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.
摘要翻译：半导体器件包括：第一和第二输入/输出端子; 连接到第一输入/输出端的第一输入/输出线; 连接到第二输入/输出端子的第二输入/输出线; 以及连接第一输入/输出线和第二输入/输出线的第一旁路路径。当处于正常操作模式时，第一个旁路路由被设置为非导通状态。当处于测试模式时，将第一旁路路径设置为导通状态，使得输入到第一输入/输出端的第一数据作为第一数据输出到第二输入/输出线，并且使得输入到所述第一输入/输出端的第二数据作为所述第一输入/输出线的第二输入数据被输出，以对应于所述第二输入/输出端中的所述时钟信号的转变方向。

6. 发明申请

US20060139079A1 Delay circuit and semiconductor device 有权
标题翻译：延迟电路和半导体器件
公开(公告)号：US20060139079A1
公开(公告)日：2006-06-29
申请号：US11318526
申请日：2005-12-28
申请人： Tadashi Onodera
发明人： Tadashi Onodera
IPC分类号： H03H11/26
CPC分类号： H03K5/1506 , H03K5/15066
摘要： A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.
摘要翻译：延迟电路包括：N级电路，其具有第一级联到级联的第N级电路，输入信号被输入到第一电路和延迟了（k-1）阶段的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间由公共延迟电路通过第i电路延迟的信号，公共延迟电路连接到信号路径，而在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共延迟电路产生N次。

7. 发明授权

US06335889B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06335889B1
公开(公告)日：2002-01-01
申请号：US09688797
申请日：2000-10-17
申请人： Tadashi Onodera
发明人： Tadashi Onodera
IPC分类号： G11C700
CPC分类号： G11C7/1012 , G11C7/10 , G11C7/1018 , G11C7/1042 , G11C7/18 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device is disclosed that is capable of outputting in the fastest possible time the first of serial data that are read in bursts, despite the increase in capacity of a memory cell array. In this semiconductor memory device, for a single address access, a plurality of bits of serial data are read in a burst from a memory sub-array that is made up by memory cell arrays 11Uo and 11Ue or memory cell arrays 11Le and 11Lo. In order that the serial data that are read first are the data of bit 0 regardless of the operation mode of the semiconductor memory device, each individual memory sub-array is divided between portions for even data and portions for odd data and the even memory cell arrays 11Ue and 11Le in which the data of bit 0 are stored are arranged closer to the data amplifier than the odd memory cell arrays 11Uo and 11Lo. The maximum length of I/O lines that are used in reading even data is therefore about half that of the maximum length of I/O lines that are used in reading odd data.
摘要翻译：公开了一种半导体存储器件，尽管存储器单元阵列的容量增加，但能够以尽可能快的时间输出以脉冲串方式读取的第一串行数据。在该半导体存储器件中，对于单个地址存取，从由存储单元阵列11Uo和11Ue或存储单元阵列11Le和11Lo组成的存储器子阵列以脉冲串形式读取多个串行数据位。为了首先读取的串行数据是位0的数据，而与半导体存储器件的操作模式无关，每个单独的存储器子阵列被划分用于偶数据的部分和用于奇数数据的部分和偶数存储单元存储位0的数据的阵列11Ue和11Le比奇数存储单元阵列11Uo和11Lo更靠近数据放大器布置。因此，用于读取偶数据的I / O线的最大长度约为读取奇数数据时使用的I / O线的最大长度的一半。

8. 发明授权

US6084391A Bandgap reference voltage generating circuit 有权
标题翻译：带隙基准电压发生电路
公开(公告)号：US6084391A
公开(公告)日：2000-07-04
申请号：US325733
申请日：1999-06-04
申请人： Tadashi Onodera
发明人： Tadashi Onodera
IPC分类号： G05F3/02 , G05F3/24 , G05F3/26 , G05F3/16
CPC分类号： G05F3/242 , G05F3/262
摘要： In a bandgap reference voltage generating circuit having first, second and third unitary circuits connected in parallel between a power supply voltage and a ground, there is added a fourth unitary circuit including an n-channel FET turned on in response to a bias voltage applied to a gate of the n-channel FET. The second unitary circuit is connected to the fourth unitary circuit through a capacitor having one end connected to a drain of the n-channel FET. When the bias voltage is applied to turn on the n-channel FET of the fourth unitary circuit, since the potential of the one end of the capacitor is dropped, a gate potential of n-channel FETs included in the first and second unitary circuits and operating in a weak inversion condition quickly becomes definite, so that a reference voltage can be generated quickly.
摘要翻译：在具有在电源电压和地之间并联连接的第一，第二和第三整体电路的带隙参考电压产生电路中，添加了第四单元电路，其包括响应于施加到 n沟道FET的栅极。第二单元电路通过电容器连接到第四单元电路，电容器的一端连接到n沟道FET的漏极。当施加偏置电压以接通第四单元电路的n沟道FET时，由于电容器一端的电位下降，所以包含在第一和第二单元电路中的n沟道FET的栅极电位和在弱反转条件下运行变得明确，从而可以快速产生参考电压。

9. 发明授权

US07432753B2 Delay circuit and semiconductor device 有权
标题翻译：延迟电路和半导体器件
公开(公告)号：US07432753B2
公开(公告)日：2008-10-07
申请号：US11907863
申请日：2007-10-18
申请人： Tadashi Onodera
发明人： Tadashi Onodera
IPC分类号： H03H11/26
CPC分类号： H03K5/1506 , H03K5/15066
摘要： A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.
摘要翻译：延迟电路包括：N级电路，具有级联连接的第N电路的第一电路，输入信号被输入到第一电路和延迟了（k-1）级的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间由公共延迟电路通过第i电路延迟的信号，公共延迟电路连接到信号路径，而在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共延迟电路产生N次。

10. 发明授权

US07292086B2 Delay circuit and semiconductor device 有权
标题翻译：延迟电路和半导体器件
公开(公告)号：US07292086B2
公开(公告)日：2007-11-06
申请号：US11318526
申请日：2005-12-28
申请人： Tadashi Onodera
发明人： Tadashi Onodera
IPC分类号： H03H11/26
CPC分类号： H03K5/1506 , H03K5/15066
摘要： A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.
摘要翻译：延迟电路包括：N级电路，其具有第一级联到级联的第N级电路，输入信号被输入到第一电路和延迟了（k-1）阶段的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间由公共延迟电路通过第i个电路延迟的信号，公共延迟电路连接到信号路径，在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共延迟电路产生N次。

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