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31. 发明授权

US07616493B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07616493B2
公开(公告)日：2009-11-10
申请号：US11763489
申请日：2007-06-15
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

32. 发明授权

US07236409B2 Semiconductor memory device provided with constant-current circuit having current trimming function 失效
标题翻译：具有具有电流修整功能的恒流电路的半导体存储器件
公开(公告)号：US07236409B2
公开(公告)日：2007-06-26
申请号：US11045383
申请日：2005-01-31
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C29/02 , G11C2029/5006
摘要： A semiconductor memory device includes a memory cell unit including at least one semiconductor memory cell, a voltage generating circuit which produces an operating voltage to which reference is made in performing a predetermined operation on the memory cell unit. The device further includes a constant-current circuit capable of a current trimming operation and adapted to supply a constant current to the voltage generating circuit.
摘要翻译：半导体存储器件包括存储单元单元，该存储单元单元包括至少一个半导体存储单元，产生电路的电压产生电路，该电压产生电路在对存储单元单元执行预定操作时进行参考。该装置还包括能够进行电流调整操作并适于向电压产生电路提供恒定电流的恒流电路。

33. 发明授权

US07190234B2 Current supply circuit, ring oscillator, nonvolatile semiconductor device and electronic card and electronic device 失效
标题翻译：电流供应电路，环形振荡器，非易失性半导体器件和电子卡及电子器件
公开(公告)号：US07190234B2
公开(公告)日：2007-03-13
申请号：US10930801
申请日：2004-09-01
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： H03L7/099
CPC分类号： H03K3/0322 , G11C16/30 , H03K3/011
摘要： A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.
摘要翻译：公开了一种电流供应电路，其包括第一电路，其被配置为产生相对于电源电压具有正依赖性的第一电流，并且不依赖于所使用的晶体管的温度变化和阈值，第二电路配置产生相对于电源电压具有大于第一电流的正相关性的第二电流，而不是依赖于所使用的晶体管的温度变化和阈值，以及第三电路，被配置为减去第二电流形成第一电流以产生相对于电源电压具有负依赖性的第三电流。

34. 发明申请

US20050088245A1 Current supply circuit, ring oscillator, nonvolatile semiconductor device and electronic card and electronic device 失效
标题翻译：电流供应电路，环形振荡器，非易失性半导体器件和电子卡及电子器件
公开(公告)号：US20050088245A1
公开(公告)日：2005-04-28
申请号：US10930801
申请日：2004-09-01
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/06 , G05F3/24 , G05F3/26 , G11C16/30 , H03K3/011 , H03K3/03 , H03B1/00 , H03L5/00
CPC分类号： H03K3/0322 , G11C16/30 , H03K3/011
摘要： A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.
摘要翻译：公开了一种电流供应电路，其包括第一电路，其被配置为产生相对于电源电压具有正依赖性的第一电流，并且不依赖于所使用的晶体管的温度变化和阈值，第二电路配置产生相对于电源电压具有大于第一电流的正相关性的第二电流，而不是依赖于所使用的晶体管的温度变化和阈值，以及第三电路，被配置为减去第二电流形成第一电流以产生相对于电源电压具有负依赖性的第三电流。

35. 发明授权

US06339345B1 Semiconductor device equipped with output circuit adjusting duration of high and low levels 有权
标题翻译：半导体器件配备有输出电路调节持续时间的高低电平
公开(公告)号：US06339345B1
公开(公告)日：2002-01-15
申请号：US09696048
申请日：2000-10-26
申请人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
发明人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
IPC分类号： H03L700
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/222 , G11C2207/2254 , H03K5/135 , H03K19/00384 , H03L7/00
摘要： In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.
摘要翻译：在输出电路10中，锁存电路11，相位差控制电路12和输出缓冲器电路13级联，并且DATA被锁定到锁存电路11中。复制电路20是布局模式的缩小版本输出电路10包括对应于电路11,12和13的电路21至23，并且通过延迟电路5和分频2分频器16将CLK提供给锁存电路21的数据输入作为数据。复制电路20的输出通过虚拟负载电路24和低通滤波器25提供给比较器26，其输出与参考电压Vref进行比较，以产生递增计数或递减计数脉冲。脉冲由计数器27计数，该计数器的计数被提供给相位差控制电路12及其副本22，以减小输出缓冲电路23的输出信号的上升沿和下降沿之间的相位差。

36. 发明授权

US06333658B1 Analog synchronization circuit 有权
标题翻译：模拟同步电路
公开(公告)号：US06333658B1
公开(公告)日：2001-12-25
申请号：US09707791
申请日：2000-11-08
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
IPC分类号： H03H1126
CPC分类号： H03K5/135
摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.
摘要翻译：模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电平衡延迟电路。两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。在每个电荷平衡延迟电路中提供第一和第二电容器。第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。第二电容器由第二电流源电路充电。比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

37. 发明授权

US08427885B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08427885B2
公开(公告)日：2013-04-23
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
CPC分类号： G11C8/14 , G11C7/18 , G11C8/12 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C2213/31 , G11C2213/72
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.
摘要翻译：一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及存储单元连接在第一和第二线之间。该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。存储单元通过连接到从MAT中选择的每个第一行形成页面。该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

38. 发明申请

US20110149653A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20110149653A1
公开(公告)日：2011-06-23
申请号：US13037965
申请日：2011-03-01
申请人： Hiroshi MAEJIMA , Katsuaki Isobe
发明人： Hiroshi MAEJIMA , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

39. 发明授权

US07876626B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07876626B2
公开(公告)日：2011-01-25
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

40. 发明申请

US20100020612A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100020612A1
公开(公告)日：2010-01-28
申请号：US12571800
申请日：2009-10-01
申请人： Katsuaki Isobe , Masatsugu Kojima
发明人： Katsuaki Isobe , Masatsugu Kojima
IPC分类号： G11C16/06 , G11C16/04 , G05F1/10
CPC分类号： G11C16/30 , G11C16/225
摘要： When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
摘要翻译：当电压电平检测器检测到电源电压达到需要恢复操作的恢复电压电平时，信号发生器产生用于指示恢复操作的恢复操作指令信号。如果某些操作模式在其他情况下被执行和验证，则恢复操作指令信号无效。

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