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31. 发明授权

US07518401B2 Differential clock tree in an integrated circuit 有权
标题翻译：差分时钟树在集成电路中
公开(公告)号：US07518401B2
公开(公告)日：2009-04-14
申请号：US11511973
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H01L25/00 , H03K19/177 , H03K19/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
摘要翻译：一种时钟分配网络，具有：主干线，其被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

32. 发明授权

US07372299B2 Differential clock tree in an integrated circuit 有权
标题翻译：差分时钟树在集成电路中
公开(公告)号：US07372299B2
公开(公告)日：2008-05-13
申请号：US11511779
申请日：2006-08-29
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
摘要翻译：一种时钟分配网络，具有：主干线，被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。

33. 发明授权

US07129765B2 Differential clock tree in an integrated circuit 有权
公开(公告)号：US07129765B2
公开(公告)日：2006-10-31
申请号：US10836722
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/2481
摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

34. 发明授权

US07126406B2 Programmable logic device having an embedded differential clock tree 有权
标题翻译：具有嵌入式差分时钟树的可编程逻辑器件
公开(公告)号：US07126406B2
公开(公告)日：2006-10-24
申请号：US10837009
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
发明人： Vasisht Mantra Vadi , Steven P. Young , Atul V. Ghia , Adebabay M. Bekele , Suresh M. Menon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/1774 , H03K19/17784 , H03K19/17796
摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
摘要翻译：一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

35. 发明授权

US07111220B1 Network physical layer with embedded multi-standard CRC generator 有权
标题翻译：具有嵌入式多标准CRC发生器的网络物理层
公开(公告)号：US07111220B1
公开(公告)日：2006-09-19
申请号：US10090519
申请日：2002-03-01
申请人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
发明人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6519 , H04L69/32 , H04L69/324
摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.
摘要翻译：公开了用于准备通过网络传输的数据的方法和结构。在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。物理层的CRC生成器符合多个网络通信标准。

36. 发明授权

US07061283B1 Differential clock driver circuit 有权
标题翻译：差分时钟驱动电路
公开(公告)号：US07061283B1
公开(公告)日：2006-06-13
申请号：US10836969
申请日：2004-04-30
申请人： Atul V. Ghia , Adebabay M. Bekele
发明人： Atul V. Ghia , Adebabay M. Bekele
IPC分类号： H03B1/00
CPC分类号： H04L25/0288 , H04L25/0272
摘要： A system for driving a differential signal on a signal line and converting the differential signal from a rail-to-rail differential signal to a small signal differential signal is described. An exemplary embodiment of the circuit includes a first programmable differential driver circuit receiving a differential input; a programmable delay circuit receiving the differential input and coupled to a second programmable differential driver circuit; and a summation circuit coupled to the first and second differential driver circuits.
摘要翻译：描述了用于驱动信号线上的差分信号并将差分信号从轨到轨差分信号转换为小信号差分信号的系统。电路的示例性实施例包括接收差分输入的第一可编程差分驱动器电路; 接收差分输入并耦合到第二可编程差分驱动器电路的可编程延迟电路; 以及耦合到第一和第二差分驱动器电路的求和电路。

37. 发明授权

US06963219B1 Programmable differential internal termination for a low voltage differential signal input or output buffer 有权
标题翻译：用于低电压差分信号输入或输出缓冲器的可编程差分内部端接
公开(公告)号：US06963219B1
公开(公告)日：2005-11-08
申请号：US10409891
申请日：2003-04-08
申请人： Atul V. Ghia , Ketan Sodha
发明人： Atul V. Ghia , Ketan Sodha
IPC分类号： H03K17/16 , H04L25/02
CPC分类号： H04L25/0278
摘要： A configurable low voltage differential signal (LVDS) system is located on a chip, such as a programmable logic device. The configurable LVDS system includes a pair of I/O pads, an LVDS transmitter for driving a differential output signal onto the I/O pads, an LVDS receiver for receiving a differential input signal from the I/O pads, and a termination resistor coupled across the pair of I/O pads, wherein the termination resistance can be enabled for use with either the LVDS transmitter or the LVDS receiver. Control circuitry is provided to control the selective enabling and disabling of the LVDS transmitter, the LVDS receiver and the termination resistance. This control circuitry can be configured in response to configuration data values stored on the chip.
摘要翻译：可配置的低电压差分信号（LVDS）系统位于芯片上，例如可编程逻辑器件。可配置的LVDS系统包括一对I / O焊盘，用于驱动I / O焊盘上的差分输出信号的LVDS发射器，用于从I / O焊盘接收差分输入信号的LVDS接收器，以及耦合在一对I / O焊盘之间，其中终端电阻可以被使能以与LVDS发射机或LVDS接收机一起使用。提供控制电路以控制LVDS发射器，LVDS接收器和终端电阻的选择性启用和禁用。可以响应于存储在芯片上的配置数据值来配置该控制电路。

38. 发明授权

US06960933B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06960933B1
公开(公告)日：2005-11-01
申请号：US10618146
申请日：2003-07-11
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19/177 , H04L25/45
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

39. 发明授权

US06617877B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06617877B1
公开(公告)日：2003-09-09
申请号：US10090286
申请日：2002-03-01
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

40. 发明授权

US06501677B1 Configuration memory architecture for FPGA 有权
标题翻译： FPGA配置存储器架构
公开(公告)号：US06501677B1
公开(公告)日：2002-12-31
申请号：US09825757
申请日：2001-04-03
申请人： Prasad Rau , Atul V. Ghia , Suresh M Menon
发明人： Prasad Rau , Atul V. Ghia , Suresh M Menon
IPC分类号： G11C1100
CPC分类号： H03K19/1776
摘要： A configuration memory architecture for an FPGA eliminates the need for a regular array of word lines and bit lines. The memory includes memory bytes, each of which has eight SRAM latches, a single flip-flop and a one-of-eight decoder having data input coupled to the inverting output of the flip-flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The flip-flops of all memory bytes for a logic block are coupled together in a serpentine shift register. Loading of configuration data involves shutting down all paths through the decoder, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path on each memory byte from the output of the flip-flop to the data input of the 0 latch. The process is then repeated for the seven other SRAM latch positions.
摘要翻译：用于FPGA的配置存储器架构消除了对字线和位线的规则阵列的需要。存储器包括存储器字节，每个存储器字节具有八个SRAM锁存器，单个触发器和八分之一解码器，其具有耦合到触发器的反相输出的数据输入和八个单独的数据输出，每个都是耦合到一个SRAM锁存器的数据输入。用于逻辑块的所有存储器字节的触发器在蛇形移位寄存器中耦合在一起。配置数据的加载涉及关闭通过解码器的所有路径，将每个存储器字节的“0”位SRAM锁存器的所有配置位移动到移位寄存器中，并将地址位设置为解码器，以创建导通路径每个存储器字节从触发器的输出到0个锁存器的数据输入。然后对于其他七个SRAM锁存位置重复该过程。

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