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31. 发明授权

US5055343A Patterned metallized film and method for making same 失效
标题翻译：图案化金属薄膜及其制造方法
公开(公告)号：US5055343A
公开(公告)日：1991-10-08
申请号：US355914
申请日：1989-05-23
申请人： James J. Murphy
发明人： James J. Murphy
IPC分类号： B44C1/00 , B32B15/08 , B44C1/10 , B44C3/08 , B44F1/04 , B44F7/00
CPC分类号： B44C3/08 , B44C1/105 , B44F1/04 , B44F7/00 , Y10S428/913 , Y10S428/914 , Y10T428/1438 , Y10T428/24917 , Y10T428/24934 , Y10T428/28 , Y10T428/2804 , Y10T428/2813 , Y10T428/2817 , Y10T428/2839 , Y10T428/2848 , Y10T428/31678
摘要： A patterned metallized film comprises a transparent or translucent polymeric film coated on one side with a thin coating of metal, with the metal coating and the polymeric film being bonded to each other. The metal coating has a multiplicity of fractures of different sizes distributed throughout the coating in a prescribed pattern so that the reflection of light by the fractured metal coating produces a three-dimensional illusion of the pattern when viewed through said polymeric film. The film may also include a layer of adhesive on the opposite side of the metal coating from the polymeric film, and a paper backing sheet on the opposite side of the adhesive layer from the metal coating. The fractures are preferably formed by heating the metallized film non-uniformly so that selected areas of the film expand and soften at a rate different from the rate at which other areas of said film expand and soften. The different rates of expansion and softening produce multiple fractures in the metal coating between the selected areas and the other areas, whereby the fractures replicate the desired pattern.

32. 发明申请

US20120220091A1 METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER 有权
标题翻译：制造具有厚底层氧化层的功率半导体器件的方法
公开(公告)号：US20120220091A1
公开(公告)日：2012-08-30
申请号：US13418128
申请日：2012-03-12
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L21/336 , H01L21/311
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
摘要翻译：在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括通过填充沟槽并覆盖衬底顶表面的亚大气压化学气相沉积工艺形成共形氧化膜。该方法还包括将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。

33. 发明申请

US20110244641A1 Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein 有权
标题翻译：具有低k介质的电极间介质的屏蔽栅沟槽FET
公开(公告)号：US20110244641A1
公开(公告)日：2011-10-06
申请号：US13083253
申请日：2011-04-08
申请人： James Pan , James J. Murphy
发明人： James Pan , James J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66727 , H01L29/66734
摘要： A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
摘要翻译：一种用于形成屏蔽栅极沟道场效应晶体管（FET）的方法包括在半导体区域中形成沟槽，在每个沟槽的底部形成屏蔽电极，并形成在屏蔽电极上延伸的电极间电介质（IED）。 IED可以包括低k电介质。该方法还包括在IED上的每个沟槽的上部形成栅电极。

34. 发明申请

US20110230046A1 SEMICONDUCTOR DICE WITH BACKSIDE TRENCHES FILLED WITH ELASTIC MATERIAL FOR IMPROVED ATTACHMENT, PACKAGES USING THE SAME, AND METHODS OF MAKING THE SAME 有权
标题翻译：具有用于改进附件的用弹性材料填充的背面斜面的半导体切片，使用其的包装及其制造方法
公开(公告)号：US20110230046A1
公开(公告)日：2011-09-22
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/28
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

35. 发明申请

US20110201179A1 METHOD AND STRUCTURE FOR DIVIDING A SUBSTRATE INTO INDIVIDUAL DEVICES 有权
标题翻译：将基板分解成个体设备的方法和结构
公开(公告)号：US20110201179A1
公开(公告)日：2011-08-18
申请号：US13095584
申请日：2011-04-27
申请人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
发明人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
IPC分类号： H01L21/78
CPC分类号： H01L21/78
摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.
摘要翻译：公开了一种从半导体结构获得单个管芯的方法。半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

36. 发明授权

US07936009B2 Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein 有权
标题翻译：屏蔽栅沟槽FET，其中具有低k电介质的电极间电介质
公开(公告)号：US07936009B2
公开(公告)日：2011-05-03
申请号：US12170328
申请日：2008-07-09
申请人： James Pan , James J. Murphy
发明人： James Pan , James J. Murphy
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66727 , H01L29/66734
摘要： A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in each trench over the shield electrode, and an inter-electrode dielectric (IED) comprising a low-k dielectric extends between the shield electrode and the gate electrode.
摘要翻译：屏蔽栅沟槽场效应晶体管（FET）包括延伸到半导体区域的沟槽。屏蔽电极设置在每个沟槽的底部。屏蔽电极通过屏蔽电介质与半导体区域绝缘。栅极电极设置在屏蔽电极上的每个沟槽中，并且包括低k电介质的电极间电介质（IED）在屏蔽电极和栅电极之间延伸。

37. 发明申请

US20110031596A1 NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件中的镍 - 锡焊料层
公开(公告)号：US20110031596A1
公开(公告)日：2011-02-10
申请号：US12535963
申请日：2009-08-05
申请人： Mike D. Gruenhagen , James J. Murphy , Suku Kim , Jim Pierce , William S. Beggs , Thomas P. Welch
发明人： Mike D. Gruenhagen , James J. Murphy , Suku Kim , Jim Pierce , William S. Beggs , Thomas P. Welch
IPC分类号： H01L23/495 , H01L23/498 , H01L23/488 , B23K35/22
CPC分类号： B23K35/0238 , B23K35/262 , B23K35/3033 , B23K35/325 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/04026 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/11318 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/13111 , H01L2224/13116 , H01L2224/14181 , H01L2224/16245 , H01L2224/16503 , H01L2224/29111 , H01L2224/29116 , H01L2224/32245 , H01L2224/32503 , H01L2224/73153 , H01L2224/73253 , H01L2224/81191 , H01L2224/81815 , H01L2224/83191 , H01L2224/83815 , H01L2224/9221 , H01L2224/94 , H01L2924/00013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/04941 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/3512 , Y10T428/12222 , H01L2924/00014 , H01L2924/01022 , H01L2924/01028 , H01L2224/03 , H01L2924/0105 , H01L2924/01051 , H01L2924/01047 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described.
摘要翻译：描述了包含镍钛（NiTi或TiNi）化合物或合金的半导体器件及其制造方法。这些器件包含具有集成电路的硅衬底，与衬底接触的接触层，接触层上的含TiNi的焊接层，焊接层上的氧化防止层，焊接层上的焊料凸块和引线框架或PCB连接到焊料凸块。 Ti和Ni材料在焊接层中的组合在单独的Ti和Ni材料中显示出许多特征，例如减少晶片翘曲，提高延展性以改善弹性，降低焊接层中的Ni消耗以及减少制造费用描述其他实施例。

38. 发明申请

US20100244126A1 Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET 有权
标题翻译：在栅极栅极栅极电极上形成硅化物的结构和方法
公开(公告)号：US20100244126A1
公开(公告)日：2010-09-30
申请号：US12412803
申请日：2009-03-27
申请人： Robert J. Purtell , James J. Murphy
发明人： Robert J. Purtell , James J. Murphy
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/28052 , H01L29/407 , H01L29/4933 , H01L29/66734
摘要： A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
摘要翻译：形成沟槽栅FET的方法包括以下步骤。多个沟槽形成为延伸到半导体区域中。形成在每个沟槽的相对侧壁和相邻沟槽之间的半导体区域的台面之上延伸的栅极电介质。在通过栅极电介质与半导体区域隔离的每个沟槽中形成栅电极。第二导电类型的阱区形成在半导体区域中。第一导电类型的源区形成在阱区的上部。在形成源极区域之后，在栅极电介质的每个沟槽邻接部分中的栅电极上形成自对准硅化物层。栅极电介质阻止在相邻沟槽之间的半导体区域的台面表面上形成自对准硅化物层。

39. 发明授权

US07768075B2 Semiconductor die packages using thin dies and metal substrates 有权
标题翻译：使用薄模和金属基板的半导体管芯封装
公开(公告)号：US07768075B2
公开(公告)日：2010-08-03
申请号：US11400729
申请日：2006-04-06
申请人： Hamza Yilmaz , Steven Sapp , Qi Wang , Minhua Li , James J. Murphy , John Robert Diroll
发明人： Hamza Yilmaz , Steven Sapp , Qi Wang , Minhua Li , James J. Murphy , John Robert Diroll
IPC分类号： H01L27/088
CPC分类号： H01L23/3114 , H01L23/481 , H01L24/13 , H01L24/14 , H01L24/81 , H01L25/072 , H01L2224/05568 , H01L2224/05573 , H01L2224/06102 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/1403 , H01L2224/14051 , H01L2224/1411 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.
摘要翻译：公开了一种半导体管芯封装。半导体管芯封装包括金属基板和半导体管芯，其包括第一表面，第一表面包括第一电端子，第二表面，包括第二电端子和至少一个孔。金属基板附接到第二表面。多个导电结构在半导体管芯上，并且包括设置在该至少一个孔中的至少一个导电结构。其他导电结构可以设置在半导体管芯的第一表面上。

40. 发明授权

US06444528B1 Selective oxide deposition in the bottom of a trench 失效
标题翻译：选择性氧化物沉积在沟槽的底部
公开(公告)号：US06444528B1
公开(公告)日：2002-09-03
申请号：US09640496
申请日：2000-08-16
申请人： James J. Murphy
发明人： James J. Murphy
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/42368 , H01L29/66734 , H01L29/7813 , H01L29/7827 , Y10S438/981
摘要： A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.
摘要翻译：半导体器件的栅极隔离结构及其制造方法在硅衬底中提供沟槽，其中介电层形成在沟槽的侧壁和底部上，电介质层在侧壁上具有第一厚度，第二厚度在大于第一厚度的底部。底部较厚的电介质层基本上减小了栅极电荷，从而降低了米勒电容效应，从而提高了半导体器件的效率并延长了其使用寿命。

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