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31. 发明授权

US5747831A SIC field-effect transistor array with ring type trenches and method of producing them 失效
标题翻译：具有环型沟槽的SIC场效应晶体管阵列及其制造方法
公开(公告)号：US5747831A
公开(公告)日：1998-05-05
申请号：US612906
申请日：1996-02-28
申请人： Werner Loose , Jacek Korec , Ekkehard Niemann , Alfred Boos
发明人： Werner Loose , Jacek Korec , Ekkehard Niemann , Alfred Boos
IPC分类号： H01L29/41 , H01L21/04 , H01L21/265 , H01L21/336 , H01L21/34 , H01L29/12 , H01L29/24 , H01L29/423 , H01L29/78 , H01L29/80 , H01L29/808 , H01L31/0312
CPC分类号： H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/8083
摘要： SiC field-effect transistors with source, gate and drain contacts and in which the source contacts are located on the surface of the semiconductor wafer, the drain contacts on the underside of the wafer and the gate contacts in trench-like structures. The trench-like structures surround the source electrodes of the transistors in the shape of a ring and the gate contacts are connected to each other on the floors of the trenches.
摘要翻译： PCT No.PCT / EP95 / 02496 371日期1996年2月28日 102（e）日期1996年2月28日PCT提交1995年6月27日PCT公布。出版物WO96 / 01500 日期1996年1月18日具有源极，栅极和漏极接触的SiC场效应晶体管，其中源极触点位于半导体晶片的表面上，漏极接触晶片的下侧，栅极接触在沟槽状结构。沟槽状结构围绕晶体管的源电极环形，并且栅极触点在沟槽的地板上彼此连接。

32. 发明授权

US5710444A Insulated gate bipolar transistor having a coupling element 失效
标题翻译：具有耦合元件的绝缘栅双极晶体管
公开(公告)号：US5710444A
公开(公告)日：1998-01-20
申请号：US448505
申请日：1995-06-08
申请人： Horst Neubrand , Jacek Korec , Dieter Silber
发明人： Horst Neubrand , Jacek Korec , Dieter Silber
IPC分类号： H01L29/78 , H01L29/10 , H01L29/739 , H01L29/786 , H01L29/72
CPC分类号： H01L29/1095 , H01L29/7394
摘要： The invention concerns a field-effect controlled semiconductor component with at least four regions of alternating opposite performance types: an anode-side emitter region, a first and a second base region connected to the emitter region, and a cathode-side emitter region; the cathode-side emitter region and the first base region from the source and drain of an MOS field effect transistor. The component also comprises an anode contact, a contact at the cathode-side emitter region and a control electrode contact of the MOS field effect transistor. The invention lies in the fact that a p+ region (36) which is adjacent to the cathode-side base region, separate, and accomodated in the anode-side n- base region (20), is connected via a separate component as a coupling element (80) with non-linear current/voltage characteristics to the cathode contact, the said region (36) being directly surrounded by the anode-side base region (20). When the field effect transistor is switched off the electrical potential in the area surrounding the supplementary p+ region (36) will exceed the threshold voltage of the coupling element, so that the supplementary p+ region (36) acts as a current sink by which the hole current can drain off against low resistance. A parasitic thyristor function is thus avoided.
摘要翻译： PCT No.PCT / EP93 / 03688 371日期：1995年6月8日 102（e）日期1995年6月8日PCT 1993年12月24日PCT公布。公开号WO94 / 15365 日期：1994年7月7日本发明涉及具有交替相反性能类型的至少四个区域的场效应控制半导体部件：阳极侧发射极区域，连接到发射极区域的第一和第二基极区域，侧发射区; 阴极侧发射极区域和来自MOS场效应晶体管的源极和漏极的第一基极区域。该部件还包括阳极接触，阴极侧发射区的接触和MOS场效应晶体管的控制电极接触。本发明的目的在于，与阳极侧基极区域相邻的p +区域（36）分离并容纳在阳极侧正极基极区域（20）中，经由单独的部件作为耦合元件（80）对阴极接触具有非线性电流/电压特性，所述区域（36）被阳极侧基极区域（20）直接包围。当场效应晶体管截止时，辅助p +区域（36）周围的区域中的电位将超过耦合元件的阈值电压，使得辅助p +区域（36）用作电流阱，通过该电流阱电流可以消除低电阻。因此避免了寄生晶闸管功能。

33. 发明授权

US5471075A Dual-channel emitter switched thyristor with trench gate 失效
标题翻译：双沟道发射极开关晶闸管与沟槽栅极
公开(公告)号：US5471075A
公开(公告)日：1995-11-28
申请号：US249898
申请日：1994-05-26
申请人： Mallikarjunaswamy S. Shekar , B. Jayant Baliga , Jacek Korec
发明人： Mallikarjunaswamy S. Shekar , B. Jayant Baliga , Jacek Korec
IPC分类号： H01L29/08 , H01L29/745 , H01L29/749 , H01L29/74 , H01L31/111
CPC分类号： H01L29/749 , H01L29/0839 , H01L29/7455
摘要： A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts. According to this second embodiment, a dual-channel TFET is preferably used to form a separate first conductivity type inversion-layer channel adjacent a first sidewall of the trench and a second conductivity type inversion-layer channel adjacent a second opposing sidewall of the trench. These channels provide the necessary electrical connections for both gated turn-on and turn-off control.
摘要翻译：半导体开关器件包括在半导体衬底中的多个相邻和并联连接的开关单元。每个单元包括具有浮动发射极区域的晶闸管和用于提供晶闸管的导通和截止控制的沟槽栅极场效应晶体管（TFET）。在开关器件的一个实施例中，通过使用在相应的浮置发射极区域和阴极触点之间串联形成反转层和堆叠层沟道连接的双沟道TFET来抑制寄生晶闸管闩锁。在另一个实施例中，通过连接一对相邻单元的浮置发射极区域来防止寄生晶闸管闩锁，从而消除阳极和阴极触点之间的寄生P-N-P-N路径。根据该第二实施例，优选地使用双沟道TFET来形成与沟槽的第一侧壁相邻的单独的第一导电类型反型层沟道和与沟槽的第二相对侧壁相邻的第二导电类型反型层沟道。这些通道为门控开启和关断控制提供必要的电气连接。

34. 发明授权

US09385196B2 Fast switching IGBT with embedded emitter shorting contacts and method for making same 有权
标题翻译：具有嵌入式发射极短路触点的快速开关IGBT及其制造方法
公开(公告)号：US09385196B2
公开(公告)日：2016-07-05
申请号：US13611653
申请日：2012-09-12
申请人： Jacek Korec , John Manning Savidge Neilson , Sameer Pendharkar
发明人： Jacek Korec , John Manning Savidge Neilson , Sameer Pendharkar
IPC分类号： H01L29/739 , H01L21/331 , H01L29/08 , H01L29/66
CPC分类号： H01L29/66333 , H01L21/02532 , H01L21/02595 , H01L21/32053 , H01L29/0834 , H01L29/7395
摘要： Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
摘要翻译：具有集成电路的具有集成发射极短路的高压IGBT和使用晶片接合或外延硅的外延硅的制造工艺用于控制漂移区厚度和快速开关速度。

35. 发明授权

US09324858B2 Trench-gated MIS devices 有权
标题翻译：沟通门槛MIS设备
公开(公告)号：US09324858B2
公开(公告)日：2016-04-26
申请号：US12917378
申请日：2010-11-01
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/76 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/872
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

36. 发明申请

US20100171543A1 PACKAGED POWER SWITCHING DEVICE 审中-公开
标题翻译：包装电源开关装置
公开(公告)号：US20100171543A1
公开(公告)日：2010-07-08
申请号：US12350651
申请日：2009-01-08
申请人： Jacek Korec , Christopher F. Bull , Juan Alejandro Herbsommer , David Jauregui , Christopher B. Kocon
发明人： Jacek Korec , Christopher F. Bull , Juan Alejandro Herbsommer , David Jauregui , Christopher B. Kocon
IPC分类号： H03K17/687 , H01L29/94 , H01L23/495
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/40245 , H01L2224/40247 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/49431 , H01L2224/73219 , H01L2224/73221 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/3025 , H03K17/6871 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.
摘要翻译：用于电力应用的封装开关器件包括连接在上部和下部电源轨道引线之间的至少一对功率MOSFET晶体管管芯，该对MOSFET晶体管管芯中的高端一个连接到上部电源轨道引线，并且低一对MOSFET晶体管管芯中的一侧连接到下部电源轨道引线。 MOSFET晶体管管芯中的至少一个被配置为用于垂直电流流过其中，并且在其背面具有源电极。

37. 发明申请

US20080108202A1 PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE 有权
标题翻译：精密高频电容器在半导体衬底上形成
公开(公告)号：US20080108202A1
公开(公告)日：2008-05-08
申请号：US11966965
申请日：2007-12-28
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/283
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
摘要翻译：一种在半导体衬底中制造电容器的方法。掺杂半导体衬底以具有低电阻率。与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。电容增加同时保持低有效的串联电阻。电极包括多个指状物，其与另一个电极的指状物交叉指向。电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

38. 发明授权

US07335946B1 Structures of and methods of fabricating trench-gated MIS devices 有权
标题翻译：沟槽栅MIS设备的结构和方法
公开(公告)号：US07335946B1
公开(公告)日：2008-02-26
申请号：US10898431
申请日：2004-07-22
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

39. 发明授权

US06858471B1 Semiconductor substrate with trenches for reducing substrate resistance 失效
标题翻译：具有沟槽的半导体衬底，用于降低衬底电阻
公开(公告)号：US06858471B1
公开(公告)日：2005-02-22
申请号：US10247906
申请日：2002-09-20
申请人： Jacek Korec , Robert Q. Xu , Mohammed Kasem
发明人： Jacek Korec , Robert Q. Xu , Mohammed Kasem
IPC分类号： H01L21/44 , H01L29/06 , H01L29/45 , H01L29/739 , H01L29/78
CPC分类号： H01L29/456 , H01L24/32 , H01L29/0657 , H01L29/7395 , H01L29/7802 , H01L29/7813 , H01L2924/10155 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.
摘要翻译：在本发明的一个实施例中，一种用于制造半导体器件的方法包括在基片的前侧形成有源区。然后围绕衬底的背面形成多个沟槽。银行网格分隔了沟渠。然后将导电材料施加到基板的背面。沟槽和导电材料用于降低衬底的导通电阻并提高热导率，而银栅格保持晶片的结构强度。

40. 发明授权

US06838722B2 Structures of and methods of fabricating trench-gated MIS devices 有权
标题翻译：沟槽栅MIS设备的结构和方法
公开(公告)号：US06838722B2
公开(公告)日：2005-01-04
申请号：US10104811
申请日：2002-03-22
申请人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Dorman Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L29/423 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/41 , H01L29/49 , H01L29/78 , H01L29/872 , H81L27/108
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

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