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31. 发明授权

US07745289B2 Method of forming a FET having ultra-low on-resistance and low gate charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US07745289B2
公开(公告)日：2010-06-29
申请号：US10997818
申请日：2004-11-24
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

32. 发明授权

US07736978B2 Method of manufacturing a trench transistor having a heavy body region 有权
公开(公告)号：US07736978B2
公开(公告)日：2010-06-15
申请号：US11503506
申请日：2006-08-10
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

33. 发明申请

US20070042551A1 Method of manufacturing a trench transistor having a heavy body region 有权
标题翻译：制造具有重体区域的沟槽晶体管的方法
公开(公告)号：US20070042551A1
公开(公告)日：2007-02-22
申请号：US11503506
申请日：2006-08-10
申请人： Brian Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Probst
发明人： Brian Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Probst
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

34. 发明申请

US20050079676A1 Method of manufacturing a trench transistor having a heavy body region 有权
标题翻译：制造具有重体区域的沟槽晶体管的方法
公开(公告)号：US20050079676A1
公开(公告)日：2005-04-14
申请号：US10927788
申请日：2004-08-27
申请人： Brian Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Probst
发明人： Brian Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Probst
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

35. 发明授权

US5767550A Integrated zener diode overvoltage protection structures in power DMOS device applications 失效
标题翻译：集成齐纳二极管过电压保护结构，用于DMOS器件应用
公开(公告)号：US5767550A
公开(公告)日：1998-06-16
申请号：US731598
申请日：1996-10-16
申请人： Daniel Calafut , Izak Bencuya , Steven Sapp
发明人： Daniel Calafut , Izak Bencuya , Steven Sapp
IPC分类号： H01L27/02 , H01L29/78 , H01L23/62
CPC分类号： H01L29/7808 , H01L27/0251 , H01L27/0255 , H01L29/7811 , H01L29/402 , H01L2924/0002 , Y10S148/126 , Y10S148/174 , Y10S438/983
摘要： In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is also a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The presence of the field plate creates a special protection device similar to a zener diode, but which exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the length of the field plate. The concentration gradients under the field plate, and hence the breakdown voltage, is controlled by suitable length of the field plate and other processing conditions. A zener breakdown programmability option is implemented so that the zener breakdown voltage is varied by suitable process selection using only one additional implant, temperature cycle, and photolithographic mask. The zener diode gate protection structure formed using the field plate has a high current per unit power; therefore, a much smaller protection structure can be implemented compared to the prior art, because much more current is conducted for a given size structure.
摘要翻译：在一个实施例中，对DMOS工艺的多晶硅栅极，主体，源极和接触掩模的修改通过在栅极下方注入阳极区域而在栅极焊盘之下添加源体单晶栅极保护二极管。阳极通过焊盘中的栅极金属连接到栅极。除了栅极 - 源极二极管之外，还存在从漏极到栅极通过由栅极下方的主体区域形成的阳极的连接。该实施例包括结终止场板。场板的存在创建了类似于齐纳二极管的特殊保护装置，但其具有类似于晶闸管的电流/电压特性。该实施例的显着特征在于，通过对制造工艺的简单修改容易地调整齐纳击穿电压。场板产生具有由场板长度确定的间距的两个相对的接合点。场板下的浓度梯度，因此击穿电压由场板的适当长度和其他处理条件控制。实施齐纳击穿可编程性选项，使得仅使用一个附加植入物，温度循环和光刻掩模的合适的工艺选择来改变齐纳击穿电压。使用场板形成的齐纳二极管栅极保护结构具有每单位功率的高电流; 因此，与现有技术相比，可以实现更小的保护结构，因为针对给定的尺寸结构进行更多的电流。

36. 发明授权

US5665619A Method of fabricating a self-aligned contact trench DMOS transistor structure 失效
标题翻译：制造自对准接触沟槽DMOS晶体管结构的方法
公开(公告)号：US5665619A
公开(公告)日：1997-09-09
申请号：US645446
申请日：1996-05-13
申请人： Sze-Hon Kwan , Izak Bencuya
发明人： Sze-Hon Kwan , Izak Bencuya
IPC分类号： H01L21/336 , H01L29/45 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7813 , H01L29/456
摘要： A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.
摘要翻译：沟槽DMOS晶体管结构包括与沟槽自对准的晶体管源极和主体的接触。通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。因此，可以减小沟槽边缘之间的距离。结果，晶体管的封装密度急剧增加。这在低m电阻和更高的电流驱动能力方面产生了大大改进的性能。提供了用于制造自对准接触结构的交替工艺模块。

37. 发明授权

US5567634A Method of fabricating self-aligned contact trench DMOS transistors 失效
标题翻译：制造自对准接触沟槽DMOS晶体管的方法
公开(公告)号：US5567634A
公开(公告)日：1996-10-22
申请号：US431765
申请日：1995-05-01
申请人： Francois Hebert , Sze-Hon Kwan , Izak Bencuya
发明人： Francois Hebert , Sze-Hon Kwan , Izak Bencuya
IPC分类号： H01L21/336 , H01L29/45 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7813 , H01L29/456
摘要： A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.
摘要翻译：制造沟槽DMOS晶体管结构的方法导致与晶体管的源极和主体与沟槽自对准的接触。通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。因此，可以减小沟槽边缘之间的距离。结果，晶体管的封装密度急剧增加。这在低导通电阻和更高的电流驱动能力方面产生了大大改进的性能。在形成用于自接触接触的氧化物间隔物之前，工艺流程使沟槽多晶硅栅极的高度最大化，从而确保间隔物的足够的台阶高度。

38. 发明授权

US4779123A Insulated gate transistor array 失效
标题翻译：绝缘栅晶体管阵列
公开(公告)号：US4779123A
公开(公告)日：1988-10-18
申请号：US808904
申请日：1985-12-13
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L29/78 , H01L21/336 , H01L27/04 , H01L29/10 , H01L29/417 , H01L27/10
CPC分类号： H01L29/1095
摘要： An insulated gate transistor (70) modified to increase its latching current density. On one side of gate (22), a high conductivity collector well (76) is provided to divert current which would otherwise flow through collector well (24) in a critical path (50) along source-collector junction (27), tending to forward bias the junction and cause the transistor to latch.
摘要翻译：修改为增加其锁存电流密度的绝缘栅极晶体管（70）。在栅极（22）的一侧上，提供高导电性收集阱（76）以转移电流，否则电流将沿着源极 - 集电极结（27）沿着临界路径（50）流过收集器阱（24），倾向于正向偏置接点并导致晶体管锁存。

39. 发明授权

US4692780A Junction field effect transistor and method of fabricating 失效
标题翻译：结型场效应晶体管及其制造方法
公开(公告)号：US4692780A
公开(公告)日：1987-09-08
申请号：US861681
申请日：1986-05-12
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L21/335 , H01L29/772 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/7722
摘要： Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, the source ridges, and the substrate.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻率硅的衬底上生长高电阻率N型硅的外延层。外延层的表面涂覆有氮化硅，部分氮化硅被去除，并且蚀刻硅以形成具有插入的硅脊的平行凹槽。施加氮化硅层，然后除去沟槽的侧壁之外。在凹槽底部的暴露的硅转化为二氧化硅，以在沟槽中形成二氧化硅层。剩余的氮化硅被去除。 P型导电性材料被离子注入到交替（栅极）脊中并且扩散以形成在相邻沟槽中的二氧化硅的横向下方延伸的栅极区域。 N型导电性材料被离子注入在中间（源极）的顶部。将金属触点施加到栅极脊，源极和基板。

40. 发明授权

US4651407A Method of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formation 失效
标题翻译：利用外延生长和垂直结形成制造结型场效应晶体管的方法
公开(公告)号：US4651407A
公开(公告)日：1987-03-24
申请号：US731685
申请日：1985-05-08
申请人： Izak Bencuya
发明人： Izak Bencuya
IPC分类号： H01L21/20 , H01L21/335 , H01L29/06 , H01L29/10 , H01L29/772 , H01L21/76
CPC分类号： H01L29/66416 , H01L29/0649 , H01L29/1066 , H01L29/7722 , Y10S148/026 , Y10S148/088 , Y10S148/111
摘要： Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions. Each gate region has portions extending laterally between the adjacent barriers and the underlying strip to form a gate junction between each portion and the N-type silicon of the second epitaxial layer. N-type conductivity imparting material is ion implanted into the intervening zones to form source regions. Metal contacts are applied to the gate regions, the source regions, and the substrate.
摘要翻译：结场效应晶体管及其制造方法。在低电阻率硅的衬底上生长高电阻率N型硅的外延层。在外延层的表面上生长一层二氧化硅，并且选择性地去除以在多个平行表面区域中以平行的二氧化硅条形状的图案露出硅。第二外延层沉积在暴露的表面区域和二氧化硅条上。在第二外延层中形成二氧化硅的阻挡层，该第二外延层从表面延伸到与掩埋条的边缘相邻但间隔开。注入P型导电性材料，然后扩散到由相邻阻挡层限定的第二外延层的区域中，并覆盖在掩埋条上以形成栅极区域。每个栅极区域具有在相邻阻挡层和下面的条带之间横向延伸的部分，以在第二外延层的每个部分和N型硅之间形成栅极结。将N型导电性材料离子注入到介入区域中以形成源区。将金属触点施加到栅极区域，源极区域和衬底。

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